Calibre IC Design & Manufacturing - Calibre IC Design & Manufacturing

Siemens acquires Canopus AI: Supercharging semiconductor manufacturing with AI-powered metrology

February 4, 2026

Siemens acquires Canopus AI to advance semiconductor manufacturing with AI-powered metrology and inspection, boosting precision, efficiency, and yield.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Calibre IC Manufacturing in 2025: The year’s biggest news

January 29, 2026

Read about 2025 highlights from Siemens Calibre IC Manufacturing group, including advances in computational metrology, monotonic machine learning, AI, EUV and GPU acceleration

By Calibre IC Design & Manufacturing

< 1 MIN READ

ESD verification in 3D ICs: Navigating unseen risks and new realities

January 21, 2026

Discover best practices for automated 3D IC ESD verification using Calibre 3DPERC. Learn how to address the unique challenges of ESD protection in advanced 3D IC designs and ensure system-level reliability.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Calibre IC Design in 2025: AI, 3D IC advancement and shift-left strategies drive verification excellence

January 12, 2026

Read about 2025 IC Design highlights from Siemens Calibre, including AI-powered verification and debug, 3D IC innovations, and shift-left strategies supporting accelerated tapeouts.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Securing your silicon: Why automated IP integrity is non-negotiable in modern SoC design

December 2, 2025

Ensure IP integrity in your SoC designs. Discover how Calibre IP Checker detects hidden IP modifications, prevents costly re-spins and accelerates tape-out.

By Calibre IC Design & Manufacturing

< 1 MIN READ

6 frequent design rule checking errors every IC designer should know – and how Calibre nmDRC helps you avoid them

November 18, 2025

Learn about some common design rule checking (DRC) violations in integrated circuit layouts—and how Calibre nmDRC helps engineers catch, analyze and resolve them quickly to ensure first-pass silicon success.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Bridging the gap: Unlock seamless collaboration in IC design with Calibre Connectivity Interface

November 5, 2025

Calibre Connectivity Interface (CCI) seamlessly connects EDA tools for advanced IC design verification. It transforms LVS into a powerful data source, enabling critical analyses like parasitic extraction & power integrity.

By Calibre IC Design & Manufacturing

< 1 MIN READ

The IC designers complete guide to design rule checking

October 30, 2025

Design rule checking (DRC) ensures IC layouts meet foundry rules. Learn how modern DRC engines like Calibre deliver scalable, sign-off accuracy at advanced nodes

By Calibre IC Design & Manufacturing

< 1 MIN READ

IC visualization: Supercharge debug of hidden parasitic threats with Calibre

October 27, 2025

By Omar Elabd If you’ve ever watched your simulation pass with flying colors, only to see your silicon fail in...

By Calibre IC Design & Manufacturing

< 1 MIN READ

From translator to powerhouse: Calibre V2LVS second generation redefines LVS verification

October 16, 2025

Explore second-generation Calibre Verilog-to-LVS: up to 4X faster runtimes, 92% less memory use, smarter debugging and robust SoC verification for advanced digital designs

By Calibre IC Design & Manufacturing

< 1 MIN READ

Design rule checking in today’s integrated circuit design environment

October 6, 2025

Explore integrated circuit design rule checking (DRC) in modern integrated circuit design, from increasing complexity to fast-feedback solutions like Calibre nmDRC Recon. Learn use cases, challenges and future trends.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Boost simulation results with powerful selective net extraction with Calibre xACT

October 1, 2025

By Karen Chow In advanced integrated circuit (IC) design, post-layout parasitic extraction is crucial for accurate performance analysis and optimization....

By Calibre IC Design & Manufacturing

< 1 MIN READ

Safeguarding IC reliability: Calibre PERC’s latch-up guard ring check

September 23, 2025

Ensure robust latch-up protection in your ICs with Calibre PERC's comprehensive ESDA verification checks. Identify and resolve issues early, improve reliability, and accelerate time-to-market.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Driving 3D IC innovation with Calibre multiphysics

September 18, 2025

Explore how Siemens EDA’s multiphysics workflow helps design teams to overcome the thermal, stress and reliability challenges of 3D ICs. Learn why early, integrated analysis with tools like Calibre 3DSTACK and Innovator3D IC is critical to success in advanced chiplet design.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Siemens-imec collaboration reduces stochastic failures in EUV lithography by orders of magnitude in wafer-level experimental validation

September 11, 2025

Siemens stochastic-aware OPC reduces EUV stochastic failures at wafer level for SRAM and logic, validating predictive modeling with experimental data.

By Calibre IC Design & Manufacturing

< 1 MIN READ

Navigating 3D IC stress: physical realities and best practices for 3D IC reliability

July 16, 2025

By Shetha Nolke As the semiconductor industry shifts toward heterogeneous 3D ICs, exciting benefits are coming within reach—from smaller footprints...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Ensure power domain compatibility by finding missing level shifters with Insight Analyzer

July 9, 2025

By Bhanu Pandey Level shifters are essential for safe, reliable mixed-signal IC design—especially as designers deploy more power domains than...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Stress less, innovate more: ensuring 3D IC reliability with Siemens Calibre 3DStress

July 2, 2025

The march toward 3D ICs and advanced packaging brings unrivaled performance and integration opportunities—but it also raises new reliability challenges...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Calibre Vision AI: a new era of fast, scalable chip-level DRC debug

June 25, 2025

By James Paris As chip designs grow more complex and SoCs reach new heights in size and integration, the challenges...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Enhancing EUV lithography resolution at high numerical aperture

June 6, 2025

By Ethan Maguire As the semiconductor industry continues to push the boundaries of feature size and density, the need for...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Overcoming noise challenges in analog and RF circuit design with Calibre PERC net shielding

May 20, 2025

By Hossam Sarhan Communication has become the backbone of everything from personal routines to industry, and the demand for analog...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Calibre xACT takes a hybrid approach to parasitic extraction

May 12, 2025

By Mark Tawfik Parasitic extraction plays a pivotal role in the design and optimization of integrated circuits (ICs). Extraction involves...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Smart strategies for metal fill extraction

April 29, 2025

By Shehab Ashraf As semiconductor technology continues to scale, the impact of parasitic effects from metal fill structures has become...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Solving inter-domain leakage challenges: Enhancing IC design with Insight Analyzer

April 10, 2025

By Charlie Olson Design reliability remains a top priority for engineers in the world of semiconductor technology. One critical challenge...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Smarter DRC for complex designs: Accelerating verification with Calibre nmDRC Recon

April 2, 2025

By John Ferguson The challenge: Traditional DRC can’t keep up… Increasing complexity and automation in IC design have made traditional...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Easily manage multiple verification jobs with Calibre

March 19, 2025

Calibre Multiple Job Submission GUI helps you optimize your IC design verification As the complexity of integrated circuits (ICs) continues...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Siemens shines at the 2025 SPIE Advanced Lithography + Patterning symposium

March 13, 2025

The SPIE Advanced Lithography + Pattering symposiums were held 23-27 February this year with the usual enthusiastic and sizable attendance...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Solving IR drop and layout bottlenecks: How Calibre DesignEnhancer streamlines IC design

March 12, 2025

By Jeff Wilson As an IC designer, you know that achieving an optimal layout is about more than just meeting...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Transforming pre-layout IC reliability analysis with Siemens Insight Analyzer

January 22, 2025

By Matthew Hogan As the industry continues to push the boundaries of what’s possible in IC design, the need for...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Unlocking post-tapeout flow scalability and performance with cloud computing

January 8, 2025

By Bassem Riad As process geometries continue to shrink, computational lithography demands increasingly powerful and abundant CPU resources to support...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Siemens EDA and TSMC partner to advance 3D IC Design

December 18, 2024

As the semiconductor industry continues to push the boundaries of innovation, the need for advanced 3D IC design solutions has...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Shift left with Calibre interactive symmetry checking to improve design efficiency

December 10, 2024

By Sara Khalaf Symmetry plays a crucial role in IC design by ensuring balanced device behavior, minimizing mismatch, and improving...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Navigating ESD challenges in 2.5D/3D ICs: A guide to robust automated verification

November 19, 2024

By Dina Medhat Electrostatic discharge (ESD) events cause severe damage to unprotected integrated circuits (ICs). ESD events cause severe damage...

By Calibre IC Design & Manufacturing

< 1 MIN READ

An introduction to advanced verification techniques for IC design symmetry

November 13, 2024

By Jonathan Muirhead Integrated circuit (IC) design, particularly for analog and radio frequency (RF) circuits, involves meticulous attention to detail...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Siemens Calibre 3DThermal wins 2024 WEAA award for innovation in 3D IC thermal analysis

November 12, 2024

Siemens Digital Industries Software’s Calibre® 3DThermal tool was awarded the 2024 AspenCore World Electronics Achievement Award (WEAA) in the EDA/IP/Software...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Dr. Fedor Pikus cultivates engineering talent in Armenia

November 7, 2024

The semiconductor market depends on the work of talented engineers, but the supply of qualified engineers worldwide hasn’t kept pace...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Shift left in IC design: A holistic strategy for faster, smarter verification

October 30, 2024

By Michael White and David Abercrombie As IC design complexity continues to grow, companies are turning to the shift left...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Tom Quan is now officially retired from TSMC

October 22, 2024

For those of us in Semiconductor Ecosystem, watching the TSMC OIP (Open Innovation Platform) evolve from a fledgling foundry event...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Enhanced short isolation process for faster circuit verification

October 21, 2024

By Ritu Walia Repetitive layout vs. schematic (LVS) runs can significantly delay project timelines. A huge number of shorted nets...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Unveiling the future of 3DIC design with Calibre 3DThermal

October 9, 2024

By Lee Wang The semiconductor industry is undergoing a transformative shift from traditional 2D integrated circuit (IC) designs to more...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Navigating the complex world of resistance extraction for curvilinear shapes in IC designs

September 26, 2024

By Nada Tarek As integrated circuit (IC) designs continue to push the boundaries of what’s possible, we’re seeing an explosion...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Optimal ESD protection with Calibre PERC and Solido Simulation Suite

September 17, 2024

By Neel Natekar Integrated circuit (IC) reliability engineers face the dual challenge of ensuring robust electrostatic discharge (ESD) protection without...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Cloud Flight Plans enable cost-effective use of the cloud for peak productivity

September 5, 2024

By Chris Clee You might ask, “What on Earth is a Cloud Flight Plan?” It’s a collection of best practices...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Faster design verification with Calibre nmLVS Recon Compare

August 22, 2024

By Wael ElManhawy Layout versus schematic (LVS) comparison is a fundamental step in integrated circuit (IC) design verification. It ensures...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Cracking the code: ensuring reliability and performance in IC design with EM/IR analysis

August 5, 2024

By Karen Chow and Joel Mercier Integrated circuits (ICs) are everywhere, powering everything from washing machines and TVs to medical...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Shift left for more efficient block design and chip integration

July 26, 2024

Block/chip integration is a lot more complicated than it gets credit for. On the face of it, chip integration just...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Speeding up early design rule checking with Calibre nmDRC Recon

June 5, 2024

By John Ferguson and Nermeen Hossam Chip designers are very aware of how time-consuming early design rule checking (DRC) can...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Automated analysis-based layout enhancements reduce power grid voltage drops during place & route: A case study with Google

May 29, 2024

By Jeff Wilson Power isn’t just a small factor in the IC design arena—it’s a cornerstone. Design teams work to...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Accelerate IP design cycles and reduce costs with Calibre design stage verification

May 6, 2024

By Terry Meeks In the fast-paced world of semiconductor design, time is a critical asset. One way IC designers save...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Balancing performance vs. debuggability in LVS circuit verification

April 23, 2024

By Wael ElManhawy Circuit verification engineers face ever more challenges as semiconductor technology evolves towards smaller process nodes and integrated...

By Calibre IC Design & Manufacturing

< 1 MIN READ

A new physical verification reporting solution smooths the on-time tapeout effort

April 16, 2024

By Richard Yan In the intricate world of system-on-chip (SoC) development, Physical Verification (PV) reports serve as vital checkpoints throughout...

By Calibre IC Design & Manufacturing

< 1 MIN READ

How to verify well layer connectivity with soft checks

April 10, 2024

By Terry Meeks In the landscape of modern IC chip verification, ensuring the connectivity from diffusion layers to well regions...

By Calibre IC Design & Manufacturing

< 1 MIN READ

AI/ML rules at the 2024 SPIE Advanced Lithography + Patterning symposium

April 3, 2024

The SPIE Advanced Lithography + Pattering symposiums were held from 25-29 February this year with enthusiastic and sizable attendance. The...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Unlocking the future with a digital twin for semiconductor manufacturing

March 29, 2024

By Srividya Jayaram In semiconductor manufacturing, staying ahead means embracing smarter processes. The rise in demand and the need to...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Using a shift left strategy to address block/chip design challenges during design-stage verification

March 21, 2024

By David Abercrombie For IC designers, striking the right balance between tight deadlines and limited resources is a constant challenge....

By Calibre IC Design & Manufacturing

< 1 MIN READ

How to get accurate inductance extraction for superconductor ICs

March 15, 2024

By Hossam Sarhan and Dusan Petranovic Supporting the high performance and reliability needed for artificial intelligence (AI), data centers and...

By Calibre IC Design & Manufacturing

< 1 MIN READ

The secret to Calibre software quality – AnaCov, our in-house code coverage analysis tool

March 7, 2024

By Mustafa Naeem, Ahmed Tahoon, Omar Ragi, and Reem El-Adawi In the realm of software testing, accurately tracking and analyzing...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Unraveling the 3DIC shift left strategy: Navigating the world of multi-dimensional ICs

February 22, 2024

By John Ferguson IC design’s evolution continues to push the boundaries of Moore’s law to new heights. One of the...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Mastering parasitic extraction at the 3 nm process node

February 13, 2024

By Dilan Heredia and Karen Chow Designing integrated circuits (ICs) for the 3 nm process node poses challenges never seen...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Why PID issues matter to IC chip designers, and how to combat them

February 8, 2024

By Derong Yan Integrated circuit (IC) chip designers are constantly striving to meet ever-increasing standards of reliability and performance in...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Shifting left with Calibre solutions: Enhancing IP design flow efficiency and design quality

January 31, 2024

By Terry Meeks Designing integrated circuits (ICs) is a multifaceted task that requires the integration of various components, including intellectual...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Revolutionizing software testing: Introducing TCP-Net++

January 24, 2024

By Mohamed Abdelkarim and Reem El Adawi In the dynamic world of software development, balancing speedy delivery with quality assurance...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Streamlining IC design verification with Calibre nmLVS Recon

January 3, 2024

By Kesmat Shahin As integrated circuits (ICs) become more complex, meeting tapeout schedules has become increasingly challenging. Statistics from industry...

By Calibre IC Design & Manufacturing

< 1 MIN READ

3DICs and the multi-physics challenge

December 11, 2023

By John Ferguson Design teams have known since, well, pretty much forever that mechanical stresses and temperature changes can affect...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Elevating user experience with UX maturity models

November 29, 2023

By Kirolos George and Reem El Adawi In today’s digital landscape, user experience (UX) plays a crucial role in the...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Inspiring the next generation of EDA engineers

November 17, 2023

As the semiconductor market grows, so does the need for qualified engineers throughout the semiconductor ecosystem. Of course, the supply...

By Calibre IC Design & Manufacturing

< 1 MIN READ

How to extend DTCO for today’s competitive IC landscape

November 8, 2023

By Le Hong As semiconductor components continue to shrink, the challenges associated with design-for-manufacturing (DFM) and design-technology co-optimization (DTCO) increase....

By Calibre IC Design & Manufacturing

< 1 MIN READ

Sanity check: Will automated fill back-annotation help?

October 25, 2023

By James Paris Hey there, custom integrated circuit (IC) design engineers! If you’re knee-deep in the world of IC design,...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Streamlining semiconductor verification with the Calibre Interactive interface

October 17, 2023

By Slava Zhuchenya In the world of semiconductors, creating and verifying IC designs is no cakewalk. It’s a complex dance...

By Calibre IC Design & Manufacturing

< 1 MIN READ

IC designers: let’s talk about shift left strategies

September 28, 2023

By John Ferguson In the constantly evolving world of electronics, where demands are high for more powerful, efficient, and reliable...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Transistor-level EMIR analysis from custom design tools? It’s all about flexibility!

September 20, 2023

By Roger Kang How do you run transistor-level electromigration and voltage drop (EMIR) analysis—command line or an interactive invocation GUI?...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Save yourself the time—here’s a way for you to view native block instances from a full-chip context

September 14, 2023

By Ritu Walia Imagine this: You primarily work on the design of a sub-block of an application-specific layout design, or...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Calibre PERC checks meet Calibre RVE default views: A match made in debugging heaven?

September 6, 2023

By Neel Natekar As technology node scaling continues, integrated circuit (IC) designers are facing increasing physical verification challenges due, in...

By Calibre IC Design & Manufacturing

< 1 MIN READ

A recap of Calibre at DAC 2023

August 29, 2023

DAC is back! At least was the feeling on the floor, judging by the number of attendees we talked to,...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Updating a Calibre DesignEnhancer via insertion kit is fast and easy!

August 21, 2023

By Jimmy Tien The Calibre® DesignEnhancer Via use model provides an automated via insertion process based on foundry design rule...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Optimize metal fill insertion while protecting critical nets and devices…automatically!

August 15, 2023

By Dina Medhat Context-aware physical verification (PV) is a relatively new addition to traditional PV flows, but it has quickly...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Are you a C++ developer or programmer? You may want to read this…

August 10, 2023

By day, Fedor Pikus is head of the Advanced Projects Team in Siemens Digital Industries Software. His responsibilities include planning...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Calibre IC manufacturing research for what comes next

August 3, 2023

By Germain Fenger Director of Product Management RET modeling, Calibre Semiconductor Manufacturing Solutions There is no rest in semiconductor manufacturing....

By Calibre IC Design & Manufacturing

< 1 MIN READ

Introducing Calibre DesignEnhancer design-stage layout optimization!

July 18, 2023

By Jeff Wilson Introduced in early 2023, the Calibre DesignEnhancer tool is part of a growing suite of shift-left tools...

By Calibre IC Design & Manufacturing

< 1 MIN READ

AUA students meet Siemens EDA!

July 11, 2023

By Armen Asatryan On June 14, a group of twelve students from the American University of Armenia (AUA), several faculty...

By Calibre IC Design & Manufacturing

< 1 MIN READ

What’s all the fuss about shift left?

July 6, 2023

By Michael White and David Abercrombie In recent months, it seems as though everyone’s been talking about shift left as...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Cross-platform database validation: Don’t add applications without it!

April 25, 2023

By James Paris The OASIS* database format is a widely used industry standard in electronic design automation (EDA) software for...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Why take chances with your PV job setups when a winning alternative is available?

April 18, 2023

By Richard Yan Are you interested in optimizing your integrated circuit (IC) physical verification (PV) flows? How does automating the...

By Calibre IC Design & Manufacturing

< 1 MIN READ

How can I run reliability checks early in the design cycle?

April 11, 2023

By Hossam Sarhan and Alexandre Arriordaz With the increasing complexity of design layouts and shorter tapeout cycles, waiting until signoff...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Siemens EDA celebrates 20 years of collaboration with imec

March 28, 2023

By Germain Fenger, Director of Product Management RET modelingCalibre Semiconductor Manufacturing solutions This year marks the 20th anniversary of the...

By Calibre IC Design & Manufacturing

< 1 MIN READ

First out of the (3DIC) box: How Siemens EDA is using the TSMC 3Dblox standard to change 3DIC verification

March 27, 2023

By John Ferguson In recognition of the growing need for a more holistic approach to three-dimensional integrated circuit (3DIC) design,...

By Calibre IC Design & Manufacturing

< 1 MIN READ

A novel methodology for EM assessment in on-power grids can improve power, time-to-market, and design cost

March 10, 2023

By Valeriy Sukharev, Armen Kteyan, Jun-Ho Choy Achieving an accurate assessment of electromigration (EM)-induced failure is essential to developing a...

By Calibre IC Design & Manufacturing

< 1 MIN READ

The secret superpower of early design verification

March 2, 2023

By Kesmat Shahin How many times, as you traversed across design stages and ran countless iterations, have you wished that...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Help! I’m not an ESD expert! Reducing ESD verification complexity

February 9, 2023

By Abdellah Bakhali If you’re not an electrostatic discharge (ESD) expert (and let’s face it, most of us aren’t), verifying...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Automated common resistance checking…it’s the smart thing to do!

January 30, 2023

By Hossam Sarhan Work smarter, not harder. Isn’t that what everyone is always telling you? Of course, it’s excellent advice,...

By Calibre IC Design & Manufacturing

< 1 MIN READ

A software migration that improves productivity? The Calibre Interactive tool has a (new) GUI for that…

January 26, 2023

By Slava Zhuchenya Software migration can be a dreaded endeavor, especially for electronic design automation (EDA) tools that design companies...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Find high resistance faster in P2P violations with interactive P2P analysis

January 16, 2023

By Slava Zhuchenya So your net trace has too much parasitic resistance. Where is it coming from? You ran your...

By Calibre IC Design & Manufacturing

< 1 MIN READ

A new method of scaling and efficiency for the semi-manufacturing flow

January 9, 2023

By Beth Martin Calibre sets sail on Kubernetes While most Calibre semi-manufacturing jobs still run on on-premises compute clusters using...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Abracadabra! Clearing shorts before full-chip implementation

December 20, 2022

By James Paris and Armen Asatryan Automated short checking during implementation lets design teams quickly find and fix these errors...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Fast, efficient, productive? Your early-stage IC design physical verification can be all that…

December 14, 2022

By John Ferguson and Nermeen Hossam With each new process node comes more complex requirements needed to ensure working silicon. ...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Infineon and Siemens collaborate for innovation

December 7, 2022

By Karen Chow When Infineon needed to select a field solver for the development of their next-generation power semiconductor products,...

By Calibre IC Design & Manufacturing

< 1 MIN READ

mPower power integrity analysis solution recognized for innovation and market impact

November 30, 2022

By Joe Davis Sponsored by France’s ElectroniqueS magazine, the Electrons d’Or Award program identifies the most innovative products of the...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Struggling to verify the reliability of your multiple-power-domain designs?

November 21, 2022

By Hossam Sarhan With the growing complexity of system-on-chip designs and technology scaling, multiple power domains are needed to optimize...

By Calibre IC Design & Manufacturing

< 1 MIN READ

TSMC OIP Ecosystem Forum 2022 all wrapped up, but not gone yet…

November 17, 2022

By Calibre Design Staff 1500+ attendees! 50 technical papers (30 live, 20 online) in three separate tracks! Standing room only...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Efinix Titanium FPGAs depend on mPower power integrity analysis

November 15, 2022

By John Wagnon Efinix’s high-performance Titanium FPGAs are custom-tailored for the computing demands of mainstream applications, targeting markets from intelligent...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Plug and Play ESD protection

November 9, 2022

By Mark Tawfik Electrostatic discharge (ESD) is the discharge of static electrical current when two objects come into contact. One...

By Calibre IC Design & Manufacturing

< 1 MIN READ

AUA announces extension of collaboration with Siemens for advanced research and academic enhancement

October 31, 2022

Back in 2012, the American University of Armenia (AUA) initiated a collaborative relationship with electronic design automation (EDA) leader Mentor...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Google, AMD, and Siemens EDA walk into a cloud…

October 10, 2022

By Michael White At DAC this past July, I had the opportunity to sit down with Phil Steinke from AMD...

By Calibre IC Design & Manufacturing

< 1 MIN READ

What’s an ESD design window, and why do I care?

October 6, 2022

By Derong Yan As we move to advanced semiconductor process nodes, electrostatic discharge (ESD) issues have become more critical in...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Can you spot the difference?

September 27, 2022

By James Paris We’ve all played those “Spot the Difference” games where you look at two similar images and try...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Outta my way – electrons coming through!

September 7, 2022

By Joel Mercier and Karen Chow Ever been in a hurry to get to a meeting, but there were a...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Papers and posters and prizes…oh my! Siemens EDA at DAC59!

August 22, 2022

By Shelly Stalnaker The Design Automation Conference of 2022 has come to an end. As the dust settles, and the...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Custom & digital layout designers…Use the Calibre RealTime Platform to close DRC fixes faster.

August 8, 2022

By Srinivas Velivala Douglas Adams, who wrote The Hitchhiker’s Guide to the Galaxy, once said of deadlines, “I love deadlines....

By Calibre IC Design & Manufacturing

< 1 MIN READ

LVS Zero to Hero in 3 Easy Steps

August 3, 2022

By James Paris When it comes to system-on-chip (SoC) physical verification turnaround-time, layout vs. schematic (LVS) verification can make or...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Improve your layout load time without capital investment?

July 26, 2022

By Roger Kang How many times has this happened to you—you waited for an hour to complete the loading of...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Direct write DEF is DEFinitely the way to go for DFM back-annotation

July 18, 2022

By Armen Asatryan, James Paris DFM back-annotation to P&R Back-annotation of DFM changes to P&R databases can be a pain....

By Calibre IC Design & Manufacturing

< 1 MIN READ

Interactive symmetry checking for analog/custom ICs: Faster, easier, more accurate

July 6, 2022

By Sara Khalaf While the reliability and performance of multiple types of designs such as analog, MEMs, and image sensors...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Optimizing design implementation with Calibre LEF/DEF technology

June 22, 2022

By James Paris and Armen Asatryan Ever hear the saying “When all you have is a hammer, everything looks like...

By Calibre IC Design & Manufacturing

< 1 MIN READ

Curves ahead for IC manufacturing

June 20, 2022

By John Sturtevant It turns out that the ideal mask pattern to print such a circle is in fact a...

By Calibre IC Design & Manufacturing

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Building the bridge between GDS and OASIS

June 13, 2022

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Does your parasitic extraction work in 5G IC designs?

June 6, 2022

By Salma Ahmed and Karen Chow The next-generation 5G mobile communication network is a heterogeneous network providing significant performance advantages...

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A touchy subject: RF IC layout verification

May 24, 2022

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The mPower toolsuite wins Elektronik Product of the Year for Software Tools!!

May 12, 2022

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Smoothing the path to manufacturing success begins with CMP simulation and fill optimization

May 11, 2022

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How to get to Win-Win-Win in conflict management

May 2, 2022

By Shelly Stalnaker & Calibre Design staff Anyone who’s been through conflict management training understands the three basic scenarios. There’s...

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Innovations in physical verification tools and technologies keep the IC industry moving forward

April 20, 2022

By John Ferguson A few years ago, I was invited to present a paper discussing the advances in physical verification...

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Using machine learning to improve DFM: a case study

April 12, 2022

By Ruben Ghulghazaryan, Davit Piliposyan, Misak Shoyan Several years ago, the American University of Armenia (AUA) and Siemens EDA began...

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The path of least resistance…leads to more reliable designs

April 6, 2022

By Derong Yan Meeting tapeout schedules and performance requirements are equally critical conditions for IC design success. Now engineers can...

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Mastering RF design challenges: The role of capacitors and context-aware PEX Tools

April 4, 2022

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Accelerating IC design time to market with Calibre in the cloud

March 31, 2022

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Ease on down the road…why “ease of use” is the next big thing in EDA, and how we get there

March 16, 2022

Ease of use is an important issue when enhancing product functionality and introducing new technology. Calibre Design Systems considers ease...

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DRC voltage text annotations: Manually placed texts can be wrong!

March 14, 2022

By Abdellah Bakhali System-on-chip (SoC) designs often use multiple intellectual property (IP) blocks from multiple IP providers. Each IP provider...

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Do you trust the reliability of your 2.5D/3D IC package designs?

March 9, 2022

By Dina Medhat 2.5D/3D ICs have become an innovative solution for many design and integration challenges. Basic physical verification for...

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Reliability checking for memory circuit design doesn’t have to destroy your eyesight!

March 7, 2022

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DAC in December?? A Review of Calibre Design Solutions at DAC 2021

March 3, 2022

Did it feel a bit weird to be submitting research papers for DAC 2022 while packing to go to DAC...

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Is there a quick and easy way to calculate P2P resistance or current density between any two coordinates in my IC design layout?

February 28, 2022

By Li Li Why, yes, there is! As you know, Calibre® PERC™ logic-driven layout (LDL) current density (CD) and point-to-point...

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The “next” technology node: ready or not, here it comes

February 22, 2022

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Physical design engineers…Learn the secret to generating signoff fill in P&R and accelerating your tapeouts

February 21, 2022

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IC package designers—looking for multi-die, system-level signoff verification?

February 16, 2022

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Stronger together! Context-aware SPICE simulation combines the strengths of static and dynamic verification for faster, more precise full-chip ESD verification

January 31, 2022

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Package verification just took a big step forward…

January 18, 2022

By Armen Asatryan and John Ferguson Over a decade ago, Calibre Design Solutions moved early into defining and building physical...

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January 11, 2022

A great software program does much, much more than just execute routines. It also optimizes the use of CPU resources...

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Calibre Design Solutions takes a look back at 2021

January 4, 2022

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The most interesting man in EDA…

December 21, 2021

As the calendar year comes to a close, we face the prospect of saying goodbye to someone who has been...

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Calibre Design Solutions at Samsung SAFE Forum: technology leadership through innovation, intelligence, and integration

December 15, 2021

Since 2018, Samsung Foundry has operated their foundry ecosystem program, called SAFE™ (Samsung Advanced Foundry Ecosystem), to ensure deep collaboration...

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mPower power integrity analysis solution certified by Tower Semiconductor for advanced analog process technologies

December 8, 2021

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TSMC OIP Forum celebrates collaboration and innovation…and we have the awards to prove it!

November 29, 2021

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Samsung Foundry and Siemens EDA: Helping companies design the next generation of Performance Platforms 2.0

November 9, 2021

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Want to know what went on at the TSMC OIP Forum this year? Here’s the inside scoop…

November 3, 2021

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Fix first, finish faster!

October 28, 2021

By James Paris A few years ago, I came across some plans to build a simple bookshelf that would fit...

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In the EDA world, efficiency + ease of use = productivity (and profitability!)

October 21, 2021

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Cloud Computing Makes Overnight TAT Attainable

October 11, 2021

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Companies talk about how mPower enables their tape-out success

September 30, 2021

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We know…power integrity analysis can be a really big pain, especially for really big designs

September 28, 2021

By Joe Davis Design teams use power integrity analysis to determine if the circuits in their designs will provide the...

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Don’t like standing in lines? Get with the (right) programs!

September 24, 2021

By John Ferguson For a while, it appeared that the worst of the COVID pandemic was behind us. My mind...

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Get rid of GUI frustration and speed up your Calibre verification job submissions!

September 14, 2021

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Seeing is believing (and learning)…

August 23, 2021

Are you a visual learner? Lots of folks are—they understand and retain instructions much more easily when they can watch...

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Caution! Avoid detours when improving resistance on ESD paths

August 19, 2021

By Derong Yan As overall transistor dimensions shrink, integrated circuit (IC) chip designs become more sensitive to the damage caused...

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Custom layout designers…Want to know a secret? You can close DRC faster. A lot faster…

August 16, 2021

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Can we just agree that perception is everything? Especially in IC design?

August 4, 2021

By Dennis Joseph Is the dress black and blue, or white and gold? Is that a rabbit or a duck?...

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2.5/3D IC designers! Don’t get hung up on latch-up!

July 27, 2021

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Don’t hit a roadblock in automotive electronics reliability verification!

July 21, 2021

The recent surge in used car prices may have you wondering what is driving this upswing, and just how much...

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Efficient package delivery is not just for FedEx!

July 12, 2021

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Do you need an automated ESD verification methodology for 2.5D/3D ICs? If so, read on…

July 8, 2021

By Dina Medhat Electrostatic discharge (ESD) events cause severe damage to unprotected integrated circuits (ICs). You already know that, of...

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P&R engineers! Interested in saving (LOTS of) time in your tapeout schedules?

June 28, 2021

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Time is money…so why waste it on bad data?

June 21, 2021

By James Paris Last Saturday was my son’s birthday and we had many things to do to get ready for...

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Shining a light on silicon photonics verification

June 14, 2021

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ESD protection verification in 2.5/3D ICs is HARD (or is it?) Our on-demand webinar has the answer

June 7, 2021

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SAFE is good. SAFE awards are even better…

June 1, 2021

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Turn IC verification challenge from a hard slog into a walk in the park by using static checks

May 19, 2021

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A SAMPle of what you need to know about SAMP technology

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Realize Live + U2U: Side by Side

May 4, 2021

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Give me my space! Why high voltage and multiple power domain designs need automated context-aware spacing checks

April 20, 2021

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DFM: Still a really good thing to do!

April 14, 2021

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Collaboration and innovation thrive on diversity

April 5, 2021

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April 1, 2021

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Adaptive Patterning: Moving with the times (and technologies)

March 24, 2021

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Building a strong reliability foundation with Calibre PERC

March 9, 2021

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March 3, 2021

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Early circuit verification can get you to tapeout faster…here’s how

February 4, 2021

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Automated ESD protection verification for 2.5-3D ICs is now a reality

January 28, 2021

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Stochasticity of the input current is an important factor in accurate EM assessment for on-chip power delivery networks

January 18, 2021

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2021: Time to simplify your life (or at least your workload)?

January 14, 2021

Everyone makes resolutions for a better life at the start of a new year – why not resolve to make...

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GLOBALFOUNDRIES and Mentor Launch a New Innovative DRC+ Hotspot Solution using Machine Learning in Calibre

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Mentor receives 2020 TSMC OIP Partner of the Year awards for EDA solutions

November 30, 2020

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Verification run configurations stressing you out? Automate them!

November 12, 2020

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October 22, 2020

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Do you have a reliable automated waiver process for reliability verification?

October 13, 2020

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SAMP series finishes with SAMP cut mask decomposition techniques

September 9, 2020

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Breaking it down…How interconnect segmentation helps resolve P2P resistance errors

August 12, 2020

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VLSI optimization—a bridge too far?

August 12, 2020

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A better, faster, smarter way to insert filler cells in P&R

August 11, 2020

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Early-stage design verification slowing down your schedules? Watch our on-demand web seminar for the solution

August 4, 2020

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Can you picture your EDA in the cloud?

July 13, 2020

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Five white papers that could change your life…

July 7, 2020

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The benefits of working together: AUA and Mentor celebrate their long-term collaboration

June 15, 2020

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Fixing DFM hotspots with Calibre signoff during design implementation

June 9, 2020

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EDA in the cloud—your questions answered

June 1, 2020

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Automated common resistance checking…it’s the smart thing to do!

May 20, 2020

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Automate via insertion for improved design reliability and performance

May 15, 2020

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Mentor, AMD, and Microsoft collaborate on EDA in the cloud

May 4, 2020

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Track decomposition for SAMP processes—What you need to know

April 21, 2020

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Siemens acquires Canopus AI: Supercharging semiconductor manufacturing with AI-powered metrology

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Bridging the gap: Unlock seamless collaboration in IC design with Calibre Connectivity Interface

The IC designers complete guide to design rule checking

IC visualization: Supercharge debug of hidden parasitic threats with Calibre

From translator to powerhouse: Calibre V2LVS second generation redefines LVS verification

Design rule checking in today’s integrated circuit design environment

Boost simulation results with powerful selective net extraction with Calibre xACT

Safeguarding IC reliability: Calibre PERC’s latch-up guard ring check

Driving 3D IC innovation with Calibre multiphysics

Siemens-imec collaboration reduces stochastic failures in EUV lithography by orders of magnitude in wafer-level experimental validation

Enhancing IC Verification: Smarter solutions for faster, more reliable designs

Revolutionizing 3D IC design with integrated multiphysics verification

How to boost reliability with early-stage reliability checks

Navigating 3D IC stress: physical realities and best practices for 3D IC reliability

Ensure power domain compatibility by finding missing level shifters with Insight Analyzer

Stress less, innovate more: ensuring 3D IC reliability with Siemens Calibre 3DStress

Calibre Vision AI: a new era of fast, scalable chip-level DRC debug

Enhancing EUV lithography resolution at high numerical aperture

Overcoming noise challenges in analog and RF circuit design with Calibre PERC net shielding

Calibre xACT takes a hybrid approach to parasitic extraction

Smart strategies for metal fill extraction

Solving inter-domain leakage challenges: Enhancing IC design with Insight Analyzer

Smarter DRC for complex designs: Accelerating verification with Calibre nmDRC Recon

Easily manage multiple verification jobs with Calibre

Siemens shines at the 2025 SPIE Advanced Lithography + Patterning symposium

Solving IR drop and layout bottlenecks: How Calibre DesignEnhancer streamlines IC design

Transforming pre-layout IC reliability analysis with Siemens Insight Analyzer

Unlocking post-tapeout flow scalability and performance with cloud computing

Siemens EDA and TSMC partner to advance 3D IC Design

Shift left with Calibre interactive symmetry checking to improve design efficiency

Navigating ESD challenges in 2.5D/3D ICs: A guide to robust automated verification

An introduction to advanced verification techniques for IC design symmetry

Siemens Calibre 3DThermal wins 2024 WEAA award for innovation in 3D IC thermal analysis

Dr. Fedor Pikus cultivates engineering talent in Armenia

Shift left in IC design: A holistic strategy for faster, smarter verification

Tom Quan is now officially retired from TSMC

Enhanced short isolation process for faster circuit verification

Unveiling the future of 3DIC design with Calibre 3DThermal

Navigating the complex world of resistance extraction for curvilinear shapes in IC designs

Optimal ESD protection with Calibre PERC and Solido Simulation Suite

Cloud Flight Plans enable cost-effective use of the cloud for peak productivity

Faster design verification with Calibre nmLVS Recon Compare

Cracking the code: ensuring reliability and performance in IC design with EM/IR analysis

Shift left for more efficient block design and chip integration

Speeding up early design rule checking with Calibre nmDRC Recon

Automated analysis-based layout enhancements reduce power grid voltage drops during place & route: A case study with Google

Accelerate IP design cycles and reduce costs with Calibre design stage verification

Balancing performance vs. debuggability in LVS circuit verification

A new physical verification reporting solution smooths the on-time tapeout effort

How to verify well layer connectivity with soft checks

AI/ML rules at the 2024 SPIE Advanced Lithography + Patterning symposium

Unlocking the future with a digital twin for semiconductor manufacturing

Using a shift left strategy to address block/chip design challenges during design-stage verification

How to get accurate inductance extraction for superconductor ICs

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Unraveling the 3DIC shift left strategy: Navigating the world of multi-dimensional ICs

Mastering parasitic extraction at the 3 nm process node

Why PID issues matter to IC chip designers, and how to combat them

Shifting left with Calibre solutions: Enhancing IP design flow efficiency and design quality

Revolutionizing software testing: Introducing TCP-Net++

Streamlining IC design verification with Calibre nmLVS Recon

3DICs and the multi-physics challenge

Elevating user experience with UX maturity models

Inspiring the next generation of EDA engineers

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Sanity check: Will automated fill back-annotation help?

Streamlining semiconductor verification with the Calibre Interactive interface

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Calibre PERC checks meet Calibre RVE default views: A match made in debugging heaven?

A recap of Calibre at DAC 2023

Updating a Calibre DesignEnhancer via insertion kit is fast and easy!

Optimize metal fill insertion while protecting critical nets and devices…automatically!

Are you a C++ developer or programmer? You may want to read this…