With a focus on design verification technologies at Siemens EDA, I help manage & develop EDA and IP standards and cultivate ecosystems around our solutions.
Its always fun to take the wraps off of solutions we have been hard at work developing. The global team…
Psst! I’ll let you in on some news… While DVCon calls the free portion of the conference “Exhibits Only,” let…
As DVCon expands, we at Mentor Graphics have grown our sponsored sessions as well. Would you expect less? In DVCon’s…
UVM 1.2 Release is Imminent As vice chair of DVCon 2014, I can share with you that the Universal Verification…
One of the nice things about DVCon is the update one can get from the developers of IEEE and Accellera…
The UCIS Story There is no secret as design sizes grow it is doubly burdensome for verification. Two factors that…
Low Power Flow Kicks-off Symposium In the world of electronic design automation, as an idea takes hold and works its…
Download the standard now – at no charge The IEEE Standards Association (IEEE-SA) has published the latest UPF 2.1 standard,…
Power Aware Verification Course Modules Released I guess I could continue the puns on the low-power theme as a few…
