Its always fun to take the wraps off of solutions we have been hard at work developing. The global team of Mentor Graphics engineers have spent considerable time and energy to bring the next level of SoC design and verification productivity to what seems to be a never ending response to Moore’s Law. As silicon feature sizes get smaller, design sizes get larger and the verification problem mushrooms. But you know that. These changes are the constants that drive the need for continued innovation. Our next level of innovation for design verification is embodied in the Mentor Enterprise Verification Platform (EVP) which we recently announced.
Gary Smith recently published Keeping Up with the Emulation Market, and lays out the fact that verification platforms are unifying with emulation now a pivotal element, not just for microprocessor design success, but for Multi-Platform Based SoC design success as well. The need to bring software debug into the loop with early hardware concepts is a verification challenge that must be supported as well. Pradeep Chakraborty reported on the point made by Anil Gupta of Applied Micro at the UVM 1.2 Day in Bangalore where Anil implored “Think about the block, the subsystem and the top.” The point made was software is often overlooked or under tested prior to committing to hardware implementation implying that our focus on UVM leaves us to verify no higher than where UVM takes us – and that is not the “top” of the SoC that mandates software be part of the verification plan.
Path to Success
With the Mentor EVP, we do address these issues. We bring simulation and emulation together in a unified platform. Software debug on conceptual hardware is supported to address verification at the “top.” And even as Gary’s report concludes with a wonder about how easy access to emulation will be supported for the masses. That too is solved in the Mentor EVP using VirtuaLAB that can be hosted in data centers along with the emulator vs. complex, one-off lab setups that lock an emulator to a design and lock out your global team of software developers from collaborating. The Mentor EVP moves to emulation for the masses in a 24×7 world.
With big designs comes big data and complex debug tasks. These complex debug tasks are all easily handled by the new Mentor Visualizer Debug Environment that has native UVM and SystemVerilog class-based debug capabilities and low-power UPF debug support to easily pinpoint design errors. All of this works in both interactive and post-simulation modes for simulation and emulation. To keep the software team productive, and get to SoC signoff sooner, the innovative and new Veloce OS3 global emulation resourcing technology moves software debug think-time offline to Mentor’s Codelink software debug tool.
And there’s more! But I’ll leave that for you to discover. When you have time, visit us here, to learn more about the Mentor Enterprise Verification Platform.
Path to Standards
As the move to support Multi-Platform Based SoC evolves, so do the standards that underpin it. And as I’ve reported on the comments of others in this blog – and the understanding from our experience that UVM can only go so far in Multi-Platform Based SoC verification – we concluded the time is right for the industry to explore the need for new standards.
We announced at DVCon 2014 an offer to take our graph-based test specification into an Accellera committee to help move beyond the limitations today’s standards have. As our investment in tools, technology and platforms continues, we are keenly aware users want their design and verification data to be as portable as possible. The Accellera user community members echoed the need to discuss portable stimulus that can take you up and down the design hierarchy from block, to subsystem, to system (“top”) and support the concurrent design of hardware and software.
In support of this, Accellera approved the formation of a Portable Stimulus Specification Proposed Working Group (PWG) to study the validity and need for a portable stimulus specification. To that end, join me at the kickoff meeting to launch this activity on Wednesday, May 7, 2014 from 10:00am to 4:00pm Pacific time at the offices of Mentor Graphics in Fremont, CA USA. If you would to attend, or you would like time on the agenda to discuss technology that would advance the development of a Portable Stimulus Specification or discuss your objectives/requirements for this group, contact me and I will put you in touch with the meeting organizer. Accellera PWG meetings are open to all and do not require Accellera membership status to attend.