Thought Leadership

DVCon U.S. 2020

By Dennis Brophy

If you have not yet registered for DVCon U.S. 2020, you can do so here. If you have the time, you will find a broad array of topics from subject matter experts that make “All Access” registration a great value.  If your time is limited, DVCon U.S. offers fee-free registration to the exhibit area, keynote and panels.  Peer interactions on the latest trends in design and verification are a sure way to keep abreast of what’s new.

Tutorial Day

In Harry Foster’s last blog, he shared his observation on the Artificial Intelligence and Machine Learning (AI/ML) content for DAC 2020 and the Mentor sponsored DVCon U.S. 2020 tutorial on Application Optimized HW/SW Design & Verification of a Machine Learning SoC.  There is a surge of AI/ML designs underway that might have you ponder how to manage system optimization issues as you weigh HW/SW boundary tradeoffs.  This tutorial will explore everything from mainstream UVM RTL verification to real AI workloads that integrate AI/Deep Learning Frameworks like TensorFlow.

Tutorial Day is Thursday with many hot topics from which to choose.  Mentor is hosting lunch that day and our own Tom Fitzpatrick has some insightful observations to share with you as well.  He will also bring the latest edition of Verification Horizons  as its editor.

Accellera Day

DVCon U.S. starts off with what has generally been standards content from Accellera.  In addition to this, the conference has added some Short Workshop topics.  The morning starts with Portable Stimulus: What’s Coming in 1.1 and What it Means For You, a tutorial from the Accellera Portable Stimulus Working Group.  The Accellera sponsored lunch will continue the Portable Stimulus conversation with a panel discussion by Working Group members.

Accellera Day also delves into the methods designers use to craft more complex systems than in the past.  If the challenge to verify those systems seems daunting, one can wonder what if must be like to design them.  The Accellera sponsored short workshop on How HLS and SystemC is Delivering on its Promise of Design and Verification Productivity showcases how next generation complex designs are being crafted giving designers the needed productivity boost by raising the level of abstraction.  SystemC/C++ take center stage for this short workshop.

Functional Safety Birds-of-a-Feather

And now for something entirely new!  The Accellera Board of Directors recently approved the formation of the Functional Safety Working Group.  This team has just started its standardization journey to capture and propagate safety intent from the system down to the SoC/IP design and implementation including failure mode propagation, verification, validation, reliability and safety mechanisms.  Their work is just starting, but they want to share and discuss their plans at a Monday, March 2nd, evening Birds-of-a-Feature meeting.  This open meeting will run from 6:30-7:30pm in the San Jose Room at the conference hotel.  All are welcome, and all we ask is you register so we can accommodate your attendance.  Register here.

There’s More!

Of course there is a lot more to DVCon U.S. 2020 than the few things I have mentioned.  From Mentor’s perspective, you can read more about what we are doing at DVCon U.S. from the editors at Tech Design Forum here. The full agenda for DVCon U.S. 2020 can be found here and it is bound to hold something of interest for you.  Check it out!

See you at DVCon U.S. 2020!

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This article first appeared on the Siemens Digital Industries Software blog at