Thought Leadership

DVCon India 2019 – Let’s Meet!

By Dennis Brophy

The design and verification of electronic systems is a global activity and Accellera has responded to make the DVCon’s more locally accessible by supporting them in many different locations around the world. The next conference, DVCon India 2019, will be held 25-26 September 2019 in Bangalore, India at the Radisson Blu.

We hope to see you there!

As the design and verification community gathers to interact with industry experts; participate in tutorials and panel discussions; learn the latest in design and verification techniques from technical paper presentations and poster sessions, Mentor’s participation embeds an autonomous systems theme for you.

The keynote by Dr. Stefan Jockusch from Siemens Digital Industries Software will point to the broad implications of digitalization where the old paradigms of design and verification must change to make way for the new as today meets tomorrow. As design and verification engineers, that is your quest as well. You make today meet tomorrow. You are often asked to make the impossible, possible. You invent to make dreams real. And with all the complexity of each new design start, you may wonder what can be done to help you be more productive.

For transportation specific needs, our tutorial will show you what we are doing to address those design and verification challenges. In our featured verification session, we will show you how to start your journey to leverage and use the Accellera Portable Stimulus Standard to handle the toughest verification problems you have.

Mentor at DVCon India

Wednesday – 25 September 2019

  • Featured Keynote: Driving Digitalization With A Boundary Free Innovation Platform
    Digital twins are becoming a necessity. Autonomous driving, as an example, puts an end to the feasibility to verify the functionality of today’s and tomorrow’s vehicles through road testing. A complete virtualization of mechanical properties, physics, electronics, real-time software, down to the sensor data processing at the IC level is the only avenue to verify the safety and functionality of advanced driver assistance systems and autonomous functions.
    Room: Grand Victoria Ballroom
    Time: 11:30 AM – 12:15 PM
  • Featured Tutorial: Next Gen System Design and Verification for Transportation
    Increased intelligence and autonomy of next-generation transportation products are driving the ICs behind those moving machines to become some of the most advanced semiconductor products ever. As a result, this is disrupting how you design, verify and develop these ICs. We offer a path forward.
    Room: Grand Victoria A
    Time: 4:00 PM – 5:00 PM

Thursday – 26 September 2019

  • Featured Session: Portable Stimulus: Designing A PSS Reuse Strategy
    Learn how PSS defines high-level verification intent to create test cases targeting different execution environments, such as simulation, emulation, hardware prototypes, and real silicon. For those using SystemVerilog, UVM or C-based tests, you will gain insight on how to preserve existing tests and enable portability across blocks to SoC test benches as you begin to use this new standard.
    Room: Grand Victoria B
    Time: 2:00 PM – 3:30 PM
    More about DVCon India 2019

More about DVCon India

As a user-led conference with user judged content you get an event that is most relevant to your daily work and insightful to advance your technical skills to apply to you current or next project. The DVCon India committee has packed a lot into just two days!  You can find more detailed information about the conference here along with registration information to attend. Mentor will have an exhibition stand (booth #15) which we will be at each day starting at 11:00 AM running until the end of the conference each day.  Please stop by to say hello.

I also encourage you to connect with the organizing committee members as well to help shape the future DVCon India content.  They encourage input to help make the next DVCon India even better.

See you at DVCon India!

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This article first appeared on the Siemens Digital Industries Software blog at