Easier UVM Testbench Construction – UVM Sequence Layering

UVM_Logo UVM Layering Package updated from OVM Layering Package

In an earlier blog post, I discussed a sequence layering technique that Mentor verification technologists had created and presented on at DVCon 2010, based on OVM.  This package has been updated and tested to work with UVM 1.0 EA and is ready for download.

As a reminder, the UVM Layering 1.0 Package, like the OVM one, provides the means to add layers of tests (sequences) without modifying the underlying testbench and without extending components or using the factory to override implementations.  The package also provides the DVCon paper and presentation that describes it in more detail in case you did not attend DVCon.

Users have found layered sequences can make verification life easier as sequences and sequencers are natively parallel and have arbitration and other communication process hooks already built-in.  The package is a companion to the UVM 2.0 Register Package that was also updated from OVM to UVM.

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/verificationhorizons/2010/05/28/uvm-layered-sequences/