Some people think UVM Testbench Debug is a drag. But really, it depends. I think it’s a day at the…
A few months ago I had the honor of being invited to lecture a graduate-level course on functional verification. After…
IC/ASIC Language and Library Adoption Trends This blog is a continuation of a series of blogs related to the 2018…
There’s a wonderful quote in Brian Kernighan book The Elements of Programming Style, where he says “Everyone knows that debugging…
Face facts: power supply nets are now effectively functional nets, but they are typically not defined in the design’s RTL….
ASIC/IC Language and Library Adoption Trends This blog is a continuation of a series of blogs related to the 2016…
This is the first in a series of blogs that presents the findings from our new 2016 Wilson Research Group…
As I mentioned in my last UVM post, UVM allows engineers to create modular, reusable, randomized self-checking testbenches. In that…
FPGA Language and Library Trends This blog is a continuation of a series of blogs related to the 2014 Wilson…
