Testbench - Verification Horizons

Face facts: power supply nets are now effectively functional nets, but they are typically not defined in the design’s RTL….

IC/ASIC Language and Library Adoption Trends This blog is a continuation of a series of blogs related to the 2016…

This is the first in a series of blogs that presents the findings from our new 2016 Wilson Research Group…

As I mentioned in my last UVM post, UVM allows engineers to create modular, reusable, randomized self-checking testbenches. In that…

FPGA Language and Library Trends This blog is a continuation of a series of blogs related to the 2014 Wilson…

Still having fun doing UVM and Class based debug? Maybe a debug contest will help. I had a contest with…

A colleague recently asked me: Has anything changed? Do design teams tape-out nowadays without GLS (Gate-Level Simulation)? And if so,…

SystemVerilog Testbench Debug – Are we having fun yet? Fun Debug should be fun. Watching waveforms march by, seeing ERRORS…

MENTOR GRAPHICS AT ARM TECHCON This week ARM® TechCon® 2013 is being held at the Santa Clara Convention Center from…