Still having fun doing UVM and Class based debug? Maybe a debug contest will help. I had a contest with…
A colleague recently asked me: Has anything changed? Do design teams tape-out nowadays without GLS (Gate-Level Simulation)? And if so,…
SystemVerilog Testbench Debug – Are we having fun yet? Fun Debug should be fun. Watching waveforms march by, seeing ERRORS…
MENTOR GRAPHICS AT ARM TECHCON This week ARM® TechCon® 2013 is being held at the Santa Clara Convention Center from…
It’s hard for me to believe that SystemVerilog 3.1 was released just over 10 years ago. The 3.1 version added…
Verification Techniques & Technologies Adoption Trends This blog is a continuation of a series of blogs that present the highlights…
Language and Library Trends This blog is a continuation of a series of blogs that present the highlights from the…
Testbench Characteristics and Simulation Strategies This blog is a continuation of a series of blogs that present the highlights from…
Graph-Based Intelligent Testbench Automation While intelligent testbench automation is still reasonably new when measured in EDA years, this graph-based verification…
