ASIC/IC Language and Library Adoption Trends
This blog is a continuation of a series of blogs related to the 2016 Wilson Research Group Functional Verification Study (click here). In my previous blog (click here), I focused on I various verification technology adoption trends. In this blog I plan to discuss various ASIC/IC language and library adoption trends..
Figure 1 shows the adoption trends for languages used to create RTL designs. Essentially, the adoption rates for all languages used to create RTL designs is projected to be either declining or flat over the next year.
Figure 1. ASIC/IC Languages Used for RTL Design
As previously noted, the reason some of the results sum to more than 100 percent is that some projects are using multiple languages; thus, individual projects can have multiple answers.
Figure 2 shows the adoption trends for languages used to create ASIC/IC testbenches. Essentially, the adoption rates for all languages used to create testbenches are either declining or flat. Furthermore, the data suggest that SystemVerilog adoption is starting to saturate or level off in the mid-70s range.
Figure 2. ASIC/IC Languages Used for Verification (Testbenches)
Figure 3 shows the adoption trends for various ASIC/IC testbench methodologies built using class libraries.
Figure 3. ASIC/IC Methodologies and Testbench Base-Class Libraries
Here we see a decline in adoption of all methodologies and class libraries with the exception of Accellera’s UVM, whose adoption continued to increase between 2014 and 2016. Furthermore, our study revealed that UVM is projected to continue its growth over the next year. However, like SystemVerlog, it will likely start to level off in the mid- to upper-70 percent range.
Figure 4 shows the ASIC/IC industry adoption trends for various assertion languages, and again, SystemVerilog Assertions seems to have saturated or leveled off.
Figure 4. ASIC/IC Assertion Language Adoption
In my next blog (click here) I plan to present the ASIC/IC design and verification power trends.
Quick links to the 2016 Wilson Research Group Study results
- Prologue: The 2016 Wilson Research Group Functional Verification Study
- Understanding and Minimizing Study Bias (2016 Study)
- Part 1 – FPGA Design Trends
- Part 2 – FPGA Verification Effort Trends
- Part 3 – FPGA Verification Effort Trends (Continued)
- Part 4 – FPGA Verification Effectiveness Trends
- Part 5 – FPGA Verification Technology Adoption Trends
- Part 6 – FPGA Verification Language and Library Adoption Trends
- Part 7 – ASIC/IC Design Trends
- Part 8 – ASIC/IC Resource Trends
- Part 9 – ASIC/IC Verification Technology Adoption Trends
- Part 10 – ASIC/IC Language and Library Adoption Trends
- Part 11 – ASIC/IC Power Management Trends
- Part 12 – ASIC/IC Verification Results Trends
- Conclusion: The 2016 Wilson Research Group Functional Verification Study