Part 9: The 2022 Wilson Research Group Functional Verification Study

ASIC Verification Technology Adoption Trends

This blog is a continuation of a series of blogs related to the 2022 Wilson Research Group Functional Verification Study. In my previous blog, I focused on ASIC design project resource trends. In this blog I examine ASIC project verification technology adoption trends.

Dynamic Verification Techniques

The ASIC market in the mid-2000 timeframe underwent growing pains to address increased verification complexity, predominately brought on with the adoption of SoC-class designs. This maturing of ASIC projects’ processes is clearly visible when comparing various simulation-based verification technology adoption trends from 2007 through 2022 as shown in Figure 9-1, although the overall dynamic verification technique adoption trends have remained flat for the past few studies.

Figure 9-1. ASIC Verification Technology Adoption Trends (2007-2022)

ASIC Static Verification Techniques

Figure 9-2 shows the ASIC adoption trends for formal property checking (e.g., model checking), as well as automatic formal applications. Examples of automatic formal application tools include: SoC integration connectivity checking, deadlock detection, X semantic safety checks, coverage reachability analysis, and many other properties that can be automatically extracted and then formally proven.

Figure 9-2. ASIC Formal Technology Adoption

We see in Figure 9-2 that formal property checking has grown at a .4.2% CAGR since 2012, while automatic formal applications have grown at a 6% CAGR.

Yet, in Figure 9-3 we see that there is significantly more adoption of formal property checking on designs over 10M gates.

Figure 9-3. ASIC Adoption of Formal Property Checking by Design Size

Emulation and FPGA Prototyping

The emulation and FPGA prototyping market value was estimated at $718M in 2020. Various analysts expect this category to grow in the order of 8-10% CAGR by 2024.

Historically, the simulation market has depended on processor frequency scaling as one means of continual improvement in simulation performance. However, as processor frequency scaling leveled off in the mid-2000 timeframe, simulation-based techniques were unable to keep up with today’s growing complexity. This is particularly true when simulating large designs that include both software and embedded processor core models. Hence, acceleration techniques are now required to extend SoC verification performance for very large designs. In fact, emulation and FPGA prototyping have become key platforms for SoC integration verification where both hardware and software are integrated into a system for the first time. In addition to SoC verification, emulation and FPGA prototyping are also used today as a platform for software development.

Taking a deeper dive into the data we collected from this year’s study, we decided to partition the data for emulation and FPGA prototyping adoption by design size as follows: less than 1M gates, 1M to 10M gates, 10M to 1B gates, and greater than 1B gates, as shown in Figure 9-3. Notice that the project adoption of emulation overtakes FPGA prototyping for very large designs.

Figure 9-4. Emulation & FPGA Prototyping Adoption by ASIC Design Size

It’s important to note that the percentage of project adoption of either emulation or FPGA prototyping shown in Figure 9-4 doesn’t necessarily correlate to market size in terms of revenue. That is, adoption of these technologies by a project doesn’t reveal how much adoption (e.g., how many emulators or FPGA prototyping systems were acquired by the project).

In my next blog I plan to discuss various IC/ASIC language and methodology adoption trends.

Quick links to the 2022 Wilson Research Group Study results

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/verificationhorizons/2022/12/18/part-9-the-2020-wilson-research-group-functional-verification-study-2/