Thought Leadership

UVM™ at DVCon 2012

By Dennis Brophy

“Ready, Set, Deploy”

Accellera DayThe last half year has seen a theme from Accellera Systems Initiative that declares its Universal Verification Methodology (UVM) is ready for design and verification teams to adopt. This theme started with a whitepaper from Accellera I authored with two of my peers, Stan Krolikoski from Cadence Design Systems and Yatin Trivedi from Synopsys. A day long UVM tutorial will be featured during “Accellera Day” at DVCon with the same ready, set, deploy theme. The UVM tutorial is timely as I have seen UVM gain traction as OVM users transition at the end of their projects and those who have yet to adopt a standardized methodology have likewise begun their adoption.

uvm 2The UVM tutorial starts with an introduction to UVM, concepts of structured verification methodology, base classes, resource configuration management, error handling and report generation. A section on the UVM register package will show how to create and manage stimulus and checking at the register level. Several expert users will show how this fits together in a complex SoC verification environment and relate lessons learned in preparing the transition to UVM, architecting reusable testbenches, debut techniques and use of the TLM 2.0 in real verification environment.

The tutorial will be presented by expert verification methodology architects and engineers as shown below:

Speakers: Tom Fitzpatrick Mentor Graphics Corp.
  Kathleen Meade Cadence Design Systems, Inc.
  Adiel Khan Synopsys, Inc.
  Stephen D’Onofrio Paradigm Works, Inc.
  John Aynsley Doulos
  Mark Strickland Cisco Systems, Inc.
  Vanessa Cooper Verilab, Inc.
  John Fowler Advanced Micro Devices, Inc.
  Peter J. D’Antonio The MITRE Corp.
  Justin Refice Advanced Micro Devices, Inc.

Conference attendees may choose this tutorial or if you wish to attend the tutorial only, DVCon charges a modest fee ($75.00). You can register here for the day long UVM tutorial.

More UVM News

With 33 exhibitors at DVCon and the heavy functional verification content, what other venue could deliver the potential of breaking UVM news? I invite you to stop by the Mentor Graphics booth were we can share with you the latest in support of UVM. You will find us at booth 801.

I look forward to seeing everyone at DVCon!

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This article first appeared on the Siemens Digital Industries Software blog at