Join us for the Verification Academy Live Seminar on Enterprise Debug & Analysis
Your designs are larger and more complex than ever and your verification solutions are generating more information that needs to be managed and analyzed. Your need to build and validate systems with pre-built design IP that comes from multiple sources places time-to-market burdens on you that need to be addressed. Your ability to debug your system from the design described in RTL running on simulation farms to emulators and FPGA prototypes with eventual debug of post silicon implementation drives even more complexity. And in the face of the adoption of newer methodologies like UVM, often embraced in unstructured ways, poses its own productivity burdens.
This pressure shows itself in our annual semi-annual industry survey results that illustrates there are now more verification engineers than design engineers for a team (a recent phenomena) and the time spent on debug now approaches 40% of an engineer’s total project time budget.
Clearly, improving debug productivity for an enterprise flow from block to system pre-silicon verification, virtual prototyping, emulation, as well as post-silicon validation is critical to stay on schedule and at the same time meet your end product quality goals.
We invite you to join us for a comprehensive seminar to learn the very latest verification techniques to address these challenges. Harry Foster, Mentor Graphics Chief Verification Scientist, will review the 2016 Wilson Research Group Functional Verification Study in his featured keynote to open the seminar. The seminar will review enterprise-level requirements, solutions and offer additional end-user keynotes that will help address your key challenges. Click here for more information about the seminar and how to register. Event details are below:
Verification Academy Live Seminar
- Location: Santa Clara, CA USA
- Date: Thursday – October 6, 2016
- 08:30 – 09:00 Check in and Registration
- 09:00 – 09:50 Industry Trends in Today’s Functional Verification Landscape
- 09:50 – 10:10 Enterprise Verification Required
- 10:15 – 11:00 Enterprise Debug for Simulation & Formal
- 11:00 – 11:15 Break
- 11:15 – 12:00 Shortcut to Productive Enterprise Verification with VIP, a UVM framework and a configuration GUI
- 12:00 – 12:40 Lunch
- 12:40 – 13:10 User Keynote Session
- 13:10 – 13:40 Enterprise System Level Analysis
- 13:40 – 14:00 Break
- 14:00 – 14:40 System-Level Debug with Emulation
- 14:40 – 15:10 User Keynote Session
- 15:10 – 15:50 FPGA Prototyping: Maximize your Enterprise Debug Productivity
- 15:50 – 16:00 Closing Remarks and Prize Drawing