UVM: Joint Statement Issued by Mentor, Cadence & Synopsys

EDACafe Guest Blog DAC Attendees Invited to Accellera’s Breakfast sponsored by Mentor, Cadence & Synopsys

The full statement can be read at EDA Cafe, click here.

The Big-3 EDA companies point out in the statement the work within Accellera to create an interoperability guide and kit to ensure verification IP and testbenches written in either the Verification Methodology Manual (VMM) or the Open Verification Methodology (OVM) can work together.  This preserves the investments made to date by users of those two methodologies.

The joint statement also says the Accellera Universal Verification Methodology (UVM) is based on OVM 2.1.1 and firmly rooted in SystemVerilog.  While we know today UVM is OVM 2.1.1 with a few small changes or additions, it is made clear that Accellera has just begun.  What happens next is the topic of the Accellera breakfast meeting.  (Have you registered yet for it?)

The joint statement asked these questions:

  • If we fast forward by a year, what would UVM base class release X look like?
  • What features should it have to solve the problems faced a year from now? 3 years from now?
  • Are we looking at adding more of the same or make a quantum leap in our ability to deal with much larger and significantly more complex designs?
  • What specifically are we doing to improve our ability to find bugs in the design and then fix them?

What questions do you have?  If you want to share them here, please do.  If you cannot attend the breakfast in person, I’ll bring your questions along to ask and report back after DAC on what happened at the Accellera breakfast.

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