Two weeks back I shared information in a blog on collaboration between Mentor Graphics and Synopsys to reduce the number of candidate register packages being considered by the Accellera Verification IP (VIP) Technical Subcommittee (TSC). Mentor withdrew its candidate when all our requirements were able to be addressed in an update to the Synopsys RAL candidate.
As it happened, of the three major features planned for UVM 1.0, only the register package addition had multiple candidates. For the phasing and TLM2 integration, there is only one code candidate. There was no need to select from multiple candidates for them.
After we announced our collaboration with Synopsys, the next steps were to review the candidates via public review meetings and then hold an in-depth review at an Accellera VIP-TSC face-to-face meeting. The multi-day face-to-face meeting concluded on September 16th and a vote to select one of the two candidate register packages opened. That vote concluded on September 22nd with the selection of RAL, the Mentor/Synopsys collaborated candidate.
While neither candidate addressed 100% of the Accellera VIP-TSC requirements, the work now is to move in a direction where it can get closer to 100% and final approval of the UVM 1.0 standard can move this work from standards development to standards deployment.
I will update you on further UVM 1.0 developments as the code progresses to a final stage for approval. As we near that point, we will want to have early users of UVM 1.0 test it with the Questa verification platform for completeness and readiness.
As I have done in my prior blogs, I invite those who wish to participate in this work or monitor it more closely to join the committee email reflector. You can find official status on Accellera UVM development and how to join and monitor it at the committee website located at http://www.accellera.org/activities/vip.