As an annual conference, DVCon has set itself apart from others. With a high focus on the application of design and verification tools and technology the venue is a prime location to exchange best practices and learn about emerging and current standards for the practicing engineer. DVCon has also gone global to promote locally the sharing of best practices and building a wider global audience. The flag ship event, DVCon U.S. has grown into an event that brackets two days of paper and poster sessions with tutorials on sessions on emerging standards from Accellera and how-to practical information by producers and users of design automations technology. Building knowledge, skill and proficiency that can be applied in one’s design and verification engineering profession is unique. What can you learn? How can you share?
The answer to those questions has one simple answer: Attend DVCon U.S. What specifically might apply to your current engineering demands are best found examining the conference program. DVCon U.S. runs Monday – Thursday (29 February – 3 March 2016). Monday is “Accellera Day” and features a focus on emerging and popular standards. Content is geared for both beginners and advanced users. Tuesday and Wednesday will feature papers, panels, posters and keynotes. The topics will take you from system level to gates and from design to verification and hardware to software and portable stimulus to low power design. These two days are organized as more of a traditional technical conference with parallel track, complemented by sponsored lunches and afternoon/evening exhibition for tool and services suppliers to share their latest product offerings. Wednesday concludes with announcing the best paper and poster awards. But that is not the end of the conference. Thursday is “Tutorial Day.” Four parallel half-day tutorials will be presented on a variety of topics. The Mentor Graphics team has sponsored two of the tutorials, one in the morning and one in the afternoon:
- Tutorial 5: Advanced Validation and Functional Verification Techniques for Complex Low Power System-on-Chips
- Tutorial 9: Back to Basics: Doing Formal the Right Way
Low Power Tutorial: New IEEE 1801 Standard
In this blog, I would like to focus in on Tutorial 5 as it relates to one of the most daunting challenges today: low power design of SoC’s. And, this tutorial will explore how new constructs in IEEE Std. 1801™-2015 (UPF 3.0) can facilitate power modeling at high levels of abstraction and improve application of Successive Refinement methodology. At the publication of this blog, the IEEE has not yet published this new standard. It was approved at the IEEE Standards Association meeting series in December 2015. If you were a member of the IEEE ballot group or a member of the IEEE 1801 Working Group, you have a copy of the last draft of the standard and have access to all the information you might need on the new constructs that were added. For everyone else, my recommendation is to attend DVCon U.S. and this tutorial to learn more in advance of the publication from the experts who created the standard and the Successive Refinement methodology.
You can find full information about DVCon U.S. here and to join us, register here. And if your time is really limited and you can’t make the full conference, the Exhibition runs into the evening (Monday – Wednesday) for those who are local and might want to visit after work. Even better news, the Exhibits-only pass is fee free. See you there!