An Extension to UVM: The UVM Container

UVM_Logo Easier DUT to Testbench Connections

This package introduces a very simple class called uvm_container. In this package Mentor shows how to use this class to link a Design Under Test (DUT) and a testbench.  The UVM Container can be downloaded here as a companion to the Accellera UVM 1.0 EA.

This extension also introduces the dual top methodology. This methodology isolates the connections between the DUT and interface in a protocol module as well as provide a convenient site to add protocol specific assertions.  These protocol modules automatically register the virtual interface with the UVM configuration using the uvm_container so that they can be used later by the testbench.

A technical paper, UVM Configuration and Virtual Interfaces, accompanies the UVM Container extension in the docs directory.  The paper explores some more complex issues related to the best use of the configuration in the context of large, scalable testbenches. The two examples provide small but sufficiently complicated examples of this methodology.

This package will be of interest to anyone who has struggled to find a consistent and scalable methodology to integrate a DUT and testbench using the UVM configuration mechanism.  It has been built to work with UVM 1.0 EA.

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This article first appeared on the Siemens Digital Industries Software blog at https://blogs.sw.siemens.com/verificationhorizons/2010/05/21/uvm-container/