Verification Methodology

Filter by:
SystemVerilog Race Condition Challenge Responses

SystemVerilog Race Condition Challenge Responses

August 13, 2020

As promised, here is my response to Siemens EDA’s SystemVerilog Race Condition Challenge. Race #1 Blocking and non-blocking assignments  …

By Dave Rich
5 MIN READ
Dawn of the new Mixed-Signal Verification Era and the need for revolutionary AMS Verification solution

Dawn of the new Mixed-Signal Verification Era and the need for revolutionary AMS Verification solution

February 8, 2019

I have been following and attending leading industry events focused on Semiconductor industry such as Hot Chips & MWC and…

By Sathishkumar Balasubramanian
3 MIN READ
Upcoming Wilson Research Group Functional Verification Study Web Seminar

Upcoming Wilson Research Group Functional Verification Study Web Seminar

October 4, 2018

About every two years, Mentor, A Siemens Business, commissions Wilson Research Group to conduct a broad, vendor-independent study of design…

By Harry Foster
< 1 MIN READ
Verification Academy’s DAC Must See Recommendations

Verification Academy’s DAC Must See Recommendations

June 18, 2018

This year the Verification Academy is celebrating two big events at DAC 2018. First, this is the Verification Academy’s tenth…

By Harry Foster
4 MIN READ
A glimpse into the journey of DVCon India 2017

A glimpse into the journey of DVCon India 2017

September 5, 2017

Time sure does fly, DVCon India 2017 is just around the corner, but I feel like DVCon India 2016 just…

By Pradeep Salla
3 MIN READ
Part 6: The 2016 Wilson Research Group Functional Verification Study

Part 6: The 2016 Wilson Research Group Functional Verification Study

September 21, 2016

FPGA Language and Library Trends This blog is a continuation of a series of blogs related to the 2016 Wilson…

By Harry Foster
5 MIN READ
No to Know VIP – Part 3

No to Know VIP – Part 3

November 16, 2015

Thus far we have talked about the importance of having a VIP which is easy to connect to the DUT…

By Pradeep Salla
4 MIN READ
Part 6: The 2014 Wilson Research Group Functional Verification Study

Part 6: The 2014 Wilson Research Group Functional Verification Study

June 3, 2015

FPGA Verification Language and Library Adoption Trends This blog is a continuation of a series of blogs related to the…

By Harry Foster
4 MIN READ
Is Gate-Level Simulation Still Required Nowadays??

Is Gate-Level Simulation Still Required Nowadays??

February 26, 2015

A colleague recently asked me: Has anything changed? Do design teams tape-out nowadays without GLS (Gate-Level Simulation)? And if so,…

By Gordon Allan
4 MIN READ