Thought Leadership

SystemVerilog Standard Updated

By Dennis Brophy

The latest revision to the SystemVerilog standard, IEEE 1800™-2017 was approved at the December 2017 IEEE Standards Association meeting series.  Since the last revision of the standard in 2012, the SystemVerilog Working Group has focused on stability of the standard to address minor errata and clarifications for the 2017 standard and defer enhancements to the next revision.  The SystemVerilog Working Group maintains an issue report database of resolved and open issues that is open for public inspection.  With continued user input, there are many things which the SystemVerilog users would like us to address.

Fee-Free Download

With about 50,000 fee-free downloads of the past standards to date, we anticipate Accellera will add this revision to continue the support of global fee-free access.  The 2017 version is available for download.  It is anticipated the 2017 revision will be available before DVCon U.S. around mid-February.  I will update this blog with download information when available.

SystemVerilog Chair Recognized

While the formal administrative details for the approval of SystemVerilog 2017 were underway, the IEEE Design Automation Standards Committee (DASC) awarded the SystemVerilog Working Group chair, Karen Pieper, with its “Ron Waxman DASC Meritorious Service Award.”  Chair Pieper has led the latest three revisions of the standard and was recognized for her outstanding service to the design and verification community.  The annual IEEE-SA awards ceremony recognized many for a broad set of standards stewardship with details on this here.

IEEE-SA Awardees – Karen Pieper, SystemVerilog WG Chair, lower left

It has been a privilege and honor to work with the whole SystemVerilog WG as secretary and to have collaborated with Karen Pieper and Working Group leadership these past few revisions.  This is a well earned and deserved recognition for Karen and she has my congratulations.

What’s Next?

I look forward to continued collaboration with the SystemVerilog community on the next revision.  But first, as mentioned before, we are waiting for the publication of IEEE Std. 1800™-2017.  We anticipate this shortly and before DVCon U.S. which is being held February 26 – March 1 in San Jose, CA USA. Chair Pieper has also been in contact with the SystemVerilog leadership team to work on plans to discuss the next revision.  Maybe we can gather in and around DVCon U.S. to start this discussion with a larger number of interested parties.  As plans for a meeting mature, I will share them as well.

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This article first appeared on the Siemens Digital Industries Software blog at