FPGA Verification Maturity: A Quantitative Analysis

In early February, I had the honor of keynoting the FPGA-forum held in the beautiful…

AI/ML at DVCon: From Theory to Application

For many years computer systems have augmented CPUs with special purpose accelerators that are targeted…

Next Generation System Design and Verification for Transportation

DVCon U.S. 2019 Tutorial When the choice to use an older or newer car presents…

Portable Stimulus Standard – In Use Now

Explore it with Tom Fitzpatrick For those who struggle with the daunting challenges to verify…

No One Expects Gate Level CDC Verification and Glitch Detection for ASIC Signoff!

[Preface: at the upcoming DVCon 2018 in San Jose, poster 4.12 addresses some of the…

See You at DVCon U.S. 2018!

We hope to see you at DVCon U.S. 2018.  Mentor will showcase 17 papers and…

SystemVerilog Standard Updated

The latest revision to the SystemVerilog standard, IEEE 1800™-2017 was approved at the December 2017…

DVCon U.S.

There is certainly demand for what the Accellera DVCon events bring the global design and…

DVCon US: UVM Is BIG

As I’m sure I’ve mentioned before, DVCon (in the US – I haven’t made it…