Thought Leadership

FPGA Verification Maturity: A Quantitative Analysis

By Harry Foster

In early February, I had the honor of keynoting the FPGA-forum held in the beautiful city of Trondheim, Norway. This is a yearly event serving both the Norwegian and European FPGA community and attracts FPGA-designers, project managers, technical managers, researchers, final year advanced-degree students and the major vendors.

Fast forward a month, and I was attending this year’s DVCon US 2020 when I was approached by the conference Steering Committee and asked if I could fill in for a canceled panel with an invited talk. In general, I spend months researching and preparing keynotes and invited talks to insure that they are high-quality, informative and entertaining. However, I was given a time constraint of less than 24 hours to prepare the talk. Nonetheless, I am a huge advocate of reuse in terms of increasing both design and verification productivity, and decided to apply these principles by updating my FPGA-forum keynote for the DVCon invited talk.

After presenting my talk, I was inundated with request to obtain a copy of the presentation. To address these request I decided that I would record a version of the talk and place both the video and presentation out on the Verification Academy.

My talk is titled “FPGA Verification Maturity: A Quantitative Analysis.” In this talk I provide an analysis of the state of FPGA verification based on the findings from our Wilson Research Group Functional Verification Study. This analysis provides invaluable insight into the state of today’s FPGA market in terms of both design and verification trends. What is unique about this analysis is that for the first time the impact of this growing complexity has been quantified in terms of verification effectiveness and effort.

By the way, many of my Mentor colleagues have also released their DVCon US 2020 presentations and posters out on a dedicated Verification Academy DVCon US event page. This includes the 2nd place Best Paper awarding winning paper “UVM – Stop Hitting Your Brother Coding Guidelines” by Rich Edelman and Chris Spear, as well as the 2nd place Best Paper awarding winning poster “Deadlock Verification for Dummies – The Easy Way Using SVA and Formal” by Mark Eslinger, Jeremy Levitt and Joe Hupcey III. So if you were unable to attend this year’s DVCon, check it out. And while you are at it, check out all our archived events and on-demand seminars, as well as technical courses, out on the Verification Academy!

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This article first appeared on the Siemens Digital Industries Software blog at