For many years computer systems have augmented CPUs with special purpose accelerators that are targeted at specialized tasks. Examples of these co-processors include special purpose graphics and digital signal processors. Lately there has been an interest and significant research in AI/ML-based accelerators. In fact, the number of AI/ML architecture papers that were recently submitted for review to the 2020 Design Automation Conference (DAC) continues to increase at an impressive 86 percent CAGR. For example, in 2018, 56 AI/ML architecture and system papers were submitted for review. That number grew to 92 submitted papers in 2019, and a jaw-dropping 194 submitted papers in 2020. Perhaps this should not be too big of a surprise considering that McKinsey & Company recently reported that the AI semiconductor total available market will grow at 5x the rate compared to the non-AI semiconductor market.
The interest in AI/ML solutions has moved beyond the bounds of research and has become a key component within many of today’s designs—ranging from voice and image recognition, near-real-time fraud detection, as well as optimize spectrum bandwidth dynamically for efficient 5G operation. So it is only fitting that we are starting to see the emergence of AI/ML content occur at industry focused conference (beyond research), such as the Design and Verification Conference (DVCon). DVCon is the leading event covering the application of languages, tools and intellectual property for the design and verification of electronic systems and integrated circuits. And for this year’s conference I want to highlight a relevant and interesting technical tutorial titled: “Application Optimized HW/SW Design & Verification of a Machine Learning SoC,” which will be held between 8:30am – 11:30am on Thursday March 05 at the DoubleTree Hotel, San Jose, CA.
This tutorial takes the user through the process of migrating an algorithm (such as an AI/ML algorithm) from generic software to a hardware implementation customized to the specific requirements of your system, while making intelligent trade-offs between hardware and software along the way. It will explain the tools and techniques needed to go from “Software to Systems” and cover a broad range of solutions including simulation, emulation, prototyping, and High-Level Synthesis to design and verify SoCs and the software that runs on them.
The tutorial uses an example algorithm of an AI/ML object classification accelerator that takes a live camera feed and overlays bounding boxes and labels of objects classified in the feed. It can classify 20 objects and will be implemented as a combination of hardware and a software application running on a complete embedded Linux stack. Finally, this tutorial will cover everything from traditional UVM RTL verification to complex HW/SW verification to running real AI workloads and integration with AI/Deep Learning Frameworks such as TensorFlow.
For additional information concerning this tutorial, as well as all the other interesting technical talks and panels, checkout this year’s DVCon program.
I hope to see you at this year’s conference!