With a focus on design verification technologies at Siemens EDA, I help manage & develop EDA and IP standards and cultivate ecosystems around our solutions.
Accellera to explore the need for an IP Security Assurance Standard In the era of SoC design where major design…
We hope to see you at DVCon U.S. 2018. Mentor will showcase 17 papers and posters during the conference on…
The latest revision to the SystemVerilog standard, IEEE 1800™-2017 was approved at the December 2017 IEEE Standards Association meeting series. …
Accellera Systems Initiative recently closed its public comment review period for the Portable Test and Stimulus Standard Early Adopter (EA)…
There is certainly demand for what the Accellera DVCon events bring the global design and verification engineering community. Not more…
Accellera’s Emerging Portable Stimulus Standard Is Pervasive at DAC 54 For the past few years, Accellera’s Portable Stimulus Working Group…
VIP: Accelerating SoC Design Verification Your SoC designs have grown more complex, not just by the sheer number of transistors…
Technical Program is Live For the past several months, the DVCon U.S. Steering Committee has been meeting to craft a…
Join us for the Verification Academy Live Seminar on Enterprise Debug & Analysis Your designs are larger and more complex…
