Keith Felton
What's new in Xpedition IC Packaging

What’s new in Xpedition IC Packaging VX.2.14

September 19, 2023

The new VX.2.14 release of Xpedition IC Packaging includes improvements and enhancements to both Xpedition Substrate Integrator and Xpedition Package…

By Keith Felton
2 MIN READ
system technology co-optimization

Shifting left with system technology co-optimization for IC packaging

August 17, 2023

We have witnessed and learned about the industry’s significant shift in semiconductors. The traditional approach of transistor scaling, once universally…

By Keith Felton
3 MIN READ
Illustration of an IC Package design with text that says Why are you spending 30%+ more time on semiconductor packaging design?

Why are you spending 30%+ more time on semiconductor packaging design?

May 18, 2023

Designs are just getting bigger and more complex Yes, an obvious aspect is increasing design complexity. Packages are now a…

By Keith Felton
2 MIN READ
Illustration of 3D IC design workflows

Why co-design-driven semiconductor package planning and prototyping is critical for design success

April 20, 2023

The connectivity management complexity of package assemblies where multiple chiplets/ASICs and memory are heterogeneously integrated, introduces a great deal of…

By Keith Felton
3 MIN READ
An image of a PCB with text that says IC Packaging 2.13

What’s new in Xpedition IC Packaging release VX.2.13

March 15, 2023

The Xpedition high density advanced packaging solution it is made up of two core products, Xpedition Substrate Integrator (xSI) which…

By Keith Felton
2 MIN READ
Image of a semiconductor package design

What are the top challenges of high-performance computing/AI semiconductor package design?

February 16, 2023

If you’re designing a high-performance processor-based package,  it’s common for the semiconductor package design to contain multiple logic chips that…

By Keith Felton
3 MIN READ
Illustration of a system-in-package (SiP)

How to get your system-in-packages right

January 18, 2023

People have been designing “modules” or system-in-packages (SiP) for a number of years; but in the last 3-5 years, I…

By Keith Felton
2 MIN READ
Illustration that says next generation IC Packaging part 4

The five keys to next-generation IC packaging design: Part 4

December 14, 2022

“Golden signoff” – The final step in the semiconductor packaging process In my last blog post, I talked about the…

By Keith Felton
2 MIN READ

The five keys to next-generation IC packaging design: Part 3

November 3, 2022

Scalability and range of IC packaging design solutions In my last blog, I talked about multi-domain and cross-domain integration that…

By Keith Felton
2 MIN READ