Keith Felton
Data, data, everywhere: Where did it come from, who owns it and is it the right version?

Data, data, everywhere: Where did it come from, who owns it and is it the right version?

March 10, 2026
Knowing what is in your IC package design, where it came from, and who touched it last and when, is key to being able to verify with complete certainty and traceability your design's current status. 
By Keith Felton
< 1 MIN READ
The smart path to STCO with Hierarchical Device Planning (HDP)

The smart path to STCO with Hierarchical Device Planning (HDP)

February 20, 2026
Siemens partnered with Intel Foundry to develop a STCO centric capability that enables a “smart path” to homogeneous disaggregation using Hierarchical Device Planning and parameterized pin regions.
By Keith Felton
< 1 MIN READ
Verifying your 2.5/3D IC device assembly level netlist

Verifying your 2.5/3D IC device assembly level netlist

February 4, 2026
In this blog we will introduce a new way to verify your 2.5/3D IC device assembly level netlist using formal verification that can exhaustively verify all interconnections between the chiplet blocks.
By Keith Felton
< 1 MIN READ
What is 3Dblox?

What is 3Dblox?

January 13, 2026
If you have not heard of it before, 3Dblox is an emerging standard that was first created by TSMC but is now managed by IEEE.
By Keith Felton
< 1 MIN READ
What’s New in Innovator3D IC solution suite release 2510

What’s New in Innovator3D IC solution suite release 2510

October 27, 2025
Innovator3D IC solution suite release 2510 marks a groundbreaking first release of the comprehensive Innovator3D IC solution suite.
By Keith Felton
< 1 MIN READ
What’s new in IC Packaging 2504

What’s new in IC Packaging 2504

April 24, 2025
To help design teams stay ahead of the curve, Siemens has released the comprehensive 2504 update for its Innovator3D IC (i3D) and Xpedition Package Designer (xPD) solutions.
By Keith Felton
< 1 MIN READ
Exploring TSMC InFO_oS and InFO_PoP certification

Exploring TSMC InFO_oS and InFO_PoP certification

February 28, 2025
Siemens EDA has recently achieved this certification for Xpedition Package Designer as part of the TSMC InFO_oS and InFO_PoP workflows.
By Keith Felton
< 1 MIN READ
What’s new in IC Packaging 2409

What’s new in IC Packaging 2409

September 19, 2024
The 2409 release is a landmark update in the field of electronic design automation (EDA), introducing a next-generation solution for...
By Keith Felton
< 1 MIN READ
Join us at the TSMC 2024 NA OIP Ecosystem Forum

Join us at the TSMC 2024 NA OIP Ecosystem Forum

September 18, 2024
The TSMC 2024 North America OIP (Open Innovation Platform®) Ecosystem Forum is just around the corner, and Siemens EDA is...
By Keith Felton
< 1 MIN READ
Embracing physical design IP reuse as a best practice

Embracing physical design IP reuse as a best practice

July 22, 2024
Efficiency in IC package design is becoming more important as design cycles shorten and complexity surges. One common approach to...
By Keith Felton
< 1 MIN READ
Multiplying engineering resources for efficient package substrate design

Multiplying engineering resources for efficient package substrate design

May 14, 2024
In the world of package substrate design, the age-old saying, “many hands make light work,” holds more truth than ever....
By Keith Felton
< 1 MIN READ
Managing the complexities of High Bandwidth Memory integration in high-performance computing

Managing the complexities of High Bandwidth Memory integration in high-performance computing

March 12, 2024
The utilization of High Bandwidth Memory (HBM) has become a cornerstone for high performance computing (HPC) CPUs, GPUs, and AI...
By Keith Felton
< 1 MIN READ
Navigating complexities in power delivery analysis: embracing the shift-left approach

Navigating complexities in power delivery analysis: embracing the shift-left approach

January 9, 2024
The demand for increased power and performance in semiconductor packages has surged. As more die and chiplets are integrated into...
By Keith Felton
< 1 MIN READ
Achieving substrate supplier fabrication requirements: a designer’s guide

Achieving substrate supplier fabrication requirements: a designer’s guide

December 5, 2023
Designing advanced package layouts with large areas of metal can be a daunting task, given the stringent requirements imposed by...
By Keith Felton
< 1 MIN READ
What’s new in Xpedition IC Packaging VX.2.14

What’s new in Xpedition IC Packaging VX.2.14

September 19, 2023
The new VX.2.14 release of Xpedition IC Packaging includes improvements and enhancements to both Xpedition Substrate Integrator and Xpedition Package...
By Keith Felton
< 1 MIN READ
Shifting left with system technology co-optimization for IC packaging

Shifting left with system technology co-optimization for IC packaging

August 17, 2023
We have witnessed and learned about the industry’s significant shift in semiconductors. The traditional approach of transistor scaling, once universally...
By Keith Felton
< 1 MIN READ
Why are you spending 30%+ more time on semiconductor packaging design?

Why are you spending 30%+ more time on semiconductor packaging design?

May 18, 2023
Designs are just getting bigger and more complex Yes, an obvious aspect is increasing design complexity. Packages are now a...
By Keith Felton
< 1 MIN READ
Why co-design-driven semiconductor package planning and prototyping is critical for design success

Why co-design-driven semiconductor package planning and prototyping is critical for design success

April 20, 2023
The connectivity management complexity of package assemblies where multiple chiplets/ASICs and memory are heterogeneously integrated, introduces a great deal of...
By Keith Felton
< 1 MIN READ
What’s new in Xpedition IC Packaging release VX.2.13

What’s new in Xpedition IC Packaging release VX.2.13

March 15, 2023
The Xpedition high density advanced packaging solution it is made up of two core products, Xpedition Substrate Integrator (xSI) which...
By Keith Felton
< 1 MIN READ
What are the top challenges of high-performance computing/AI semiconductor package design?

What are the top challenges of high-performance computing/AI semiconductor package design?

February 16, 2023
If you’re designing a high-performance processor-based package,  it’s common for the semiconductor package design to contain multiple logic chips that...
By Keith Felton
< 1 MIN READ
How to get your system-in-packages right

How to get your system-in-packages right

January 18, 2023
People have been designing “modules” or system-in-packages (SiP) for a number of years; but in the last 3-5 years, I...
By Keith Felton
< 1 MIN READ
The five keys to next-generation IC packaging design: Part 4

The five keys to next-generation IC packaging design: Part 4

December 14, 2022
“Golden signoff” – The final step in the semiconductor packaging process In my last blog post, I talked about the...
By Keith Felton
< 1 MIN READ
The five keys to next-generation IC packaging design: Part 3

The five keys to next-generation IC packaging design: Part 3

November 3, 2022
Scalability and range of IC packaging design solutions In my last blog, I talked about multi-domain and cross-domain integration that...
By Keith Felton
< 1 MIN READ
The five keys to next-generation IC packaging design: Part 2

The five keys to next-generation IC packaging design: Part 2

October 19, 2022
Multi-domain integration enables faster time to market for complex advanced semiconductor packages with a seamless integration of design and verification.
By Keith Felton
< 1 MIN READ
What’s new in Xpedition Advanced IC Packaging release VX.2.12

What’s new in Xpedition Advanced IC Packaging release VX.2.12

September 19, 2022
The Xpedition high density advanced packaging solution it is made up of two core products, Xpedition Substrate Integrator (xSI) which...
By Keith Felton
< 1 MIN READ
The Five Keys to Next-Generation IC Packaging Design: Part 1

The Five Keys to Next-Generation IC Packaging Design: Part 1

September 7, 2022
Part 1: An advanced IC packaging design and verification solution For many applications, next generation IC packaging is the best...
By Keith Felton
< 1 MIN READ
Megatrends of advanced IC packaging solutions 

Megatrends of advanced IC packaging solutions 

August 25, 2022
Over last 2-3 years, everyone has been talking about Moore’s “Law” becoming invalid. Even if it does, we will continue...
By Keith Felton
< 1 MIN READ
Learn about heterogeneous integration of semiconductors for autonomous driving, electric vehicle, and ADAS systems at the IESF 2022 automotive conference

Learn about heterogeneous integration of semiconductors for autonomous driving, electric vehicle, and ADAS systems at the IESF 2022 automotive conference

August 18, 2022
IESF Automotive began 22 years ago and has been a must-attend event for automotive E/E design experts and executives throughout...
By Keith Felton
< 1 MIN READ
Getting your metal fill right

Getting your metal fill right

July 14, 2022
If you’re involved in semiconductor package design using routable substrates — that is, as opposed to leadframe based — then...
By Keith Felton
< 1 MIN READ
Semiconductor package design market trends: 2023 forecast from Siemens EDA

Semiconductor package design market trends: 2023 forecast from Siemens EDA

June 29, 2022
Semiconductor package design industry in 2023 expects to see accelerated growth of heterogeneous integration resulting emergence and adoption of new technology.
By Keith Felton
< 1 MIN READ
Meeting ISO 26262 requirements just got a lot easier

Meeting ISO 26262 requirements just got a lot easier

September 17, 2018
If you are in any way involved in the automotive supply chain or ecosystem, you have heard about functional safety...
By Keith Felton
< 1 MIN READ
What’s the fastest-growing area of semiconductor packaging?

What’s the fastest-growing area of semiconductor packaging?

April 19, 2018
HDAP! No longer reliant on the mobile market alone, High Density Advanced Packaging (HDAP) has become the fastest growing and...
By Keith Felton
< 1 MIN READ
ECTC’2017 Sets Orlando Abuzz with Fan Out Wafer Level Packaging (FO-WLP) – posted on behalf of Kevin Rinebold

ECTC’2017 Sets Orlando Abuzz with Fan Out Wafer Level Packaging (FO-WLP) – posted on behalf of Kevin Rinebold

June 1, 2017
This year’s ECTC is one of the best attended in recent history that I can recall.  The hot topic is...
By Keith Felton
< 1 MIN READ
Going to DAC’2017 in Austin TX? Interested in High Density Advanced Packaging? then read on!!

Going to DAC’2017 in Austin TX? Interested in High Density Advanced Packaging? then read on!!

May 26, 2017
If you’re coming or planning on coming to DAC this June and interested in HDAP such as FO-WLP then you...
By Keith Felton
< 1 MIN READ
Stop by the Mentor booth at ECTC’2017 and talk HDAP

Stop by the Mentor booth at ECTC’2017 and talk HDAP

May 25, 2017
If you’re planning to attend ECTC’2017 next week, then stop by the Mentor booth, #521, to talk with some of...
By Keith Felton
< 1 MIN READ