The five keys to next-generation IC packaging design: Part 3

By Keith Felton

Scalability and range of IC packaging design solutions

In my last blog, I talked about multi-domain and cross-domain integration that a digital twin methodology enables. I discussed how it enables things such ECAD/MCAD, thermal/stress and package-level signal integrity analysis with parasitic simulation model extraction.  

In this blog, I will talk about scalability and range of your IC packaging design solution that is required to tackle current and future advanced semiconductor packages, and what is required for predictable precision manufacturing handoff.  

Package assembly design kit (PADK) to create scalability & range in advanced semiconductor package design

Heterogeneous packaging technologies are more complex to design, fabricate, and assemble, potentially limiting their availability to all but the leading semiconductor companies and their bleeding edge designs. Fortunately, the design and supply chain ecosystem can play a powerful role in enabling the democratization of such technologies, putting them within the reach of all designers and companies just as the silicon foundry world did with process design kits (PDK), which have become ubiquitous.  

Automated IC verification is driven by design rules created by the foundry and provided in a PDK to design houses. EDA tool suppliers qualify their toolsets against these rules to ensure their verification tools produce proven, repeatable, sign-off quality results. The purpose of a package assembly design kit (PADK) is similar to that of the PDK, to ensure manufacturability and performance using standardized rules that ensure consistency across a process.  

Obviously, a PADK must include both a physical verification and extraction signoff solution, and it should also address thermal and/or stress sign-off solutions. All these processes should be independent of any specific design tool or process used to create the assembly. In addition, a complete PADK must work across both semiconductor and packaging domains, implying that the flow must support multiple formats.  

IC packaging design challenges encountered by designers 

Finally, all these verification processes must be validated by the package assembly/OSAT company. The scale and complexity of advanced semiconductor packages puts immediate pressure on the designer and the design schedule, which often gets extended.  

An emerging popular approach to managing this is concurrent team design, where multiple designers simultaneously work on the same design across local or global networks yet retain the ability to visualize all design activity without having to endure any onerous set up or process management. 

Another common challenge is the time required for verification signoff prior to manufacture. The proven way to avoid this bottleneck and its related impacts is to implement a process and methodology of integrated and continuous verification so that the final verification signoff process is controlled and manageable. Eliminating iterations requires a design environment with the capabilities and features to meet process rules without relying on hit-or-miss manual methods that will likely require multiple design spins to achieve the handoff criteria. In order to avoid multiple design revisions to pass the manufacturer’s rules, automation is mandatory.   

If you would the read more about solution scalability and range needs then please download this paper.

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This article first appeared on the Siemens Digital Industries Software blog at