The role of AI-infused EDA solutions for semiconductor-enabled products and systems

Discover why semiconductor-enabled products and systems are demanding AI-infused solutions and how AI is changing the nature of semiconductor design.

Image showing physical design IP reuse with Xpedition Package designer

Embracing physical design IP reuse as a best practice

Efficiency in IC package design is becoming more important as design cycles shorten and complexity surges. One common approach to…

Discover how AI is changing the nature of semiconductor design

AI is shaping the semiconductor industry’s future and its alignment with Siemens’ commitment to innovation and enhancing sustainability by accelerating…

Assembly Verification Flow for Silicon Interposers with Embedded Deep Trench Capacitance

User2User 2024: Assembly verification flow for silicon interposers

In this User2User 2024 session Broadcom’s Suvarna Vikhankar presents “Assembly Verification Flow for Silicon Interposers with Embedded Deep Trench Capacitance”

New innovative way to functionally verify heterogeneous 2D/3D package connectivity

New innovative way to functionally verify heterogeneous 2D/3D package connectivity

This blog introduces a white paper that addresses the challenges of verifying
package connectivity and illustrated how to use formal tools to verify connectivity for package designs.

Two people working at a white board with text onscreen that says: Multiplying engineering resources for efficient package substrate design

Multiplying engineering resources for efficient package substrate design

In the world of package substrate design, the age-old saying, “many hands make light work,” holds more truth than ever….

Image of a chip with text that says: High Bandwidth Memory integration

Managing the complexities of High Bandwidth Memory integration in high-performance computing

The utilization of High Bandwidth Memory (HBM) has become a cornerstone for high performance computing (HPC) CPUs, GPUs, and AI…

Taking 2.5D/3D IC physical verification to the next level

Taking 2.5D/3D IC physical verification to the next level

Taking 2.5D/3D IC physical verification to the next level. As package designs continue to evolve, so must the verification requirements. Designers working on even the most complex multi-die, multi-chiplet stacked configurations require enhanced checking capabilities to quickly and easily verify that the physical die are placed correctly to ensure proper connectivity and electrical behavior.

A deep dive into HDAP LVS/LVL verification

EDA companies are developing tools and workflows to support HDAP (High-density advanced packaging) LVS/LVL verification. Though the data for achieving “signoff-level” confidence is a work in progress, EDA companies are providing tools that can adapt to different levels of data availability and enable HDAP designers to execute HDAP LVS/LVL flows that are both productive and beneficial.