Two people working at a white board with text onscreen that says: Multiplying engineering resources for efficient package substrate design

Multiplying engineering resources for efficient package substrate design

In the world of package substrate design, the age-old saying, “many hands make light work,” holds more truth than ever….

Image of a chip with text that says: High Bandwidth Memory integration

Managing the complexities of High Bandwidth Memory integration in high-performance computing

The utilization of High Bandwidth Memory (HBM) has become a cornerstone for high performance computing (HPC) CPUs, GPUs, and AI…

Taking 2.5D/3D IC physical verification to the next level

Taking 2.5D/3D IC physical verification to the next level

Taking 2.5D/3D IC physical verification to the next level. As package designs continue to evolve, so must the verification requirements. Designers working on even the most complex multi-die, multi-chiplet stacked configurations require enhanced checking capabilities to quickly and easily verify that the physical die are placed correctly to ensure proper connectivity and electrical behavior.

A deep dive into HDAP LVS/LVL verification

EDA companies are developing tools and workflows to support HDAP (High-density advanced packaging) LVS/LVL verification. Though the data for achieving “signoff-level” confidence is a work in progress, EDA companies are providing tools that can adapt to different levels of data availability and enable HDAP designers to execute HDAP LVS/LVL flows that are both productive and beneficial.

Image of a chip on a board with text that says Navigating complexities in power delivery analysis: embracing the shift-left approach

Navigating complexities in power delivery analysis: embracing the shift-left approach

The demand for increased power and performance in semiconductor packages has surged. As more die and chiplets are integrated into…

An image of an IC package design in Xpedition Package Designer with text that says: Achieving substrate supplier fabrication requirements: a designer's guide

Achieving substrate supplier fabrication requirements: a designer’s guide

Designing advanced package layouts with large areas of metal can be a daunting task, given the stringent requirements imposed by…

Image of chiplets with text onscreen saying HBM

High Bandwidth Memory (HBM): Unleashing the power of next-gen memory technology

In the ever-evolving realm of semiconductor technology, one innovation stands out above the rest: High Bandwidth Memory (HBM). Offering unparalleled…

What's new in Xpedition IC Packaging

What’s new in Xpedition IC Packaging VX.2.14

The new VX.2.14 release of Xpedition IC Packaging includes improvements and enhancements to both Xpedition Substrate Integrator and Xpedition Package…

system technology co-optimization

Shifting left with system technology co-optimization for IC packaging

We have witnessed and learned about the industry’s significant shift in semiconductors. The traditional approach of transistor scaling, once universally…