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A “big rock” approach to DC drop analysis in IC package design

The key analysis needs of high-performance computing semiconductor package design Today, power requirements are continually increasing as you bring more…

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Why are you spending 30%+ more time on semiconductor packaging design?

Designs are just getting bigger and more complex Yes, an obvious aspect is increasing design complexity. Packages are now a…

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Why co-design-driven semiconductor package planning and prototyping is critical for design success

The connectivity management complexity of package assemblies where multiple chiplets/ASICs and memory are heterogeneously integrated, introduces a great deal of…

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What’s new in Xpedition IC Packaging release VX.2.13

The Xpedition high density advanced packaging solution it is made up of two core products, Xpedition Substrate Integrator (xSI) which…

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What are the top challenges of high-performance computing/AI semiconductor package design?

If you’re designing a high-performance processor-based package,  it’s common for the semiconductor package design to contain multiple logic chips that…

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How to get your system-in-packages right

People have been designing “modules” or system-in-packages (SiP) for a number of years; but in the last 3-5 years, I…

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The five keys to next-generation IC packaging design: Part 4

“Golden signoff” – The final step in the semiconductor packaging process In my last blog post, I talked about the…

Test engineer performing design rule checks manually for 3D IC heterogenous designs

Assembly level layout vs. schematic in 3D IC design verification

In our fifth podcast on 3D IC design workflows, we discussed what a 3D IC physical design workflow looks like,…

The five keys to next-generation IC packaging design: Part 3

Scalability and range of IC packaging design solutions In my last blog, I talked about multi-domain and cross-domain integration that…