Engineer seated at computer studying physical prototype for early planning of interconnect systems and design verification workflows

Importance of early planning for interconnect verification in 3D IC physical design workflows

In our last podcast on 3D IC architecture workflows, we discussed how a system or microarchitectures determine how to partition…

The five keys to next-generation IC packaging design: Part 2

Multi-domain integration enables faster time to market for complex advanced semiconductor packages with a seamless integration of design and verification.

what's new in Xpedition IC Packaging

What’s new in Xpedition Advanced IC Packaging release VX.2.12

The Xpedition high density advanced packaging solution it is made up of two core products, Xpedition Substrate Integrator (xSI) which…

The Five Keys to Next-Generation IC Packaging Design: Part 1

Part 1: An advanced IC packaging design and verification solution For many applications, next generation IC packaging is the best…

3D IC verification requires a golden netlist that allows exceptions

With current 3D IC packaging technologies, since the system-level netlist (the 3D IC design intent) drives system-level LVS verification, designers…

IESF 2022

Learn about heterogeneous integration of semiconductors for autonomous driving, electric vehicle, and ADAS systems at the IESF 2022 automotive conference

IESF Automotive began 22 years ago and has been a must-attend event for automotive E/E design experts and executives throughout…

3D IC and the system-technology co-optimization (STCO) approach

3D IC and the system-technology co-optimization (STCO) approach

Semiconductor engineers aim to deliver best-in-class devices despite technology scaling and cost limitations of monolithic integrated circuit (IC) design. To…

What’s the current state of 3D IC design?

In the first podcast about 3D IC heterogeneous integration, we talked about the disaggregation of once monolithic implementation architectures into…

Getting your metal fill right

If you’re involved in semiconductor package design using routable substrates — that is, as opposed to leadframe based — then…