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Why Traditional PCB Methods Fall Short in 3D IC Design
In this episode of the Siemens 3D IC Podcast Series,we delve into the world of FOWLP (Fan-out wafer-level packaging) with industry expert Chris Cone. From his beginnings as an analog design engineer to his current role as an IC Packaging Product Marketing Manager at Siemens EDA, Chris shares valuable insights about this transformative technology that’s reshaping the semiconductor industry.
What is FOWLP? Fan-Out Wafer-Level Packaging explained
FOWLP is gaining rapid industry adoption as companies seek to manage increasingly complex semiconductor designs. As Chris discusses, this shift requires more sophisticated automation and cross-functional workflows than traditional packaging methods. The growing complexity and size of modern designs necessitate intelligent, automated processes that are both replayable and flexible. By implementing a common design framework with human-readable automation, teams can streamline their workflows, enable faster iterations, and improve collaboration between layout engineers, SI/PI analysts, and replay coordinators. This episode explores how:
- FOWLP enables multiple die integration with improved cost-performance ratio
- Automation is crucial for managing complex design iterations
- Design process requires intuitive, flexible, and extensible workflows
- Team collaboration framework essential for successful implementation
- Role-specific expertise must be properly matched within automation framework
Podcast highlights: FOWLP and 3D IC design insights from Siemens EDA
Episode Highlights with Timestamps:
- [00:01] Introduction and industry context for 3D IC packaging
- [01:01] Chris Cone’s background and journey in semiconductor design
- [02:02] Explanation of FOWLP technology and its advantages
- [04:20] Four major phases of FOWLP design process detailed
- [09:34] Impact on different roles and team collaboration requirements
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Complete episode transcript: What is FOWLP and why are Companies shifting to it?
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John McMillan
According to Tech Insights latest analysis, 3D IC and advanced packaging solutions now represent over 45 % of the total IC packaging marketing value, marking a fundamental shift in how the semiconductor industry approaches system integration. With that, I welcome you to the Siemens EDA podcast series where we dive into the exciting world of semiconductor chiplet integration and advanced technology platforms using 2.5 and 3D techniques brought to you by the Siemens Thought Leadership Team. I’m your host, John McMillan.
In this podcast series, I talk with industry leaders and subject matter experts to discuss the latest 3D IC chiplet ecosystems, industry trends, and roadmaps. In today’s podcast, I’m excited to be joined by Chris Cone. Chris is an IC packaging product marketing manager at Siemens EDA. And today we’re talking about fan out wafer level packaging. Welcome, Chris. Thank you for joining me today. And before we dive into today’s discussion, please tell our listeners about yourself, your current role, and your background.
Chris Cone
Yeah, I’m happy to do that and thanks for having me on this podcast, John. So I started out, I guess, several years ago as an analog design engineer. And I’ve done several flavors of design for like, I think I got the opportunity to work on the first USB transceiver that was commercially available, 1394 and a number of other types of interfaces. And from there, graduated into working in the EDA. So I joined Mentor Graphics, which is now Siemens EDA, and I got the opportunity to work with the custom IC Design Tools and do things like silicon photonics and then join the, now I’m working with the packaging team and doing all this wonderful packaging technology.
John McMillan
Awesome, thanks. So let’s start with what is fan out wafer level packaging and why are companies shifting to it?
Chris Cone
Well. Fan Out wafer level packaging, I often call it just FOWLP. It brings several die together from various processes into a compact packaging system. And there’s a number of advantages with this, including lower cost, higher performance, and you have an improved form factor. They’re very thin. And so one of things you can do is you can stack a DRAM directly on top of the processor. And so our newer smartphones, including the iPhone, will use this technology.
John McMillan
So how is this shift affecting the design process? How is it different from a traditional BGA design process?
Chris Cone
Well, I think there’s two factors that come into this. One of them is the technology complexity, and then the other is the sheer design size. And so if we apply traditional PCB methods to doing design, we end up falling short. And so we know we need to do quite a bit of automation. Automation, or significant automation, is required to complete design iterations. And the other thing you need to do is you need to do a lot of design iterations. You need to be able to explore different parameters, optimize parameters, and then generate different variants of your design. And so one of the things you need to do is when you’re developing this automation,
You need to be mindful that all these steps need to be sequenced. You need to be able to play everything from the beginning all the way through to generate your completed design. So ideally, a replay coordinator would be able to start a design replay at the end of their day, go off and have a great evening, work-life balance and all that, and then come in in the morning and see the report and see what it is that they need to do to make changes, to update it, what they need to communicate to their team to make…
make improvements to the project and to the design. And so overall I think we’re shifting quite a bit more to the IC way of thinking.
John McMillan
Can you describe what the major phases in the FOWLP design process are?
Chris Cone
Well, I see it as basically four kind of key phases in the design process. So the first thing you want to do is be able to set up your technology. And if you’re lucky, the foundry that you’re working with is going to provide a tech file, which essentially is a PDK, so that’s an IC term, Process Design Kit. So your tools will be set up. You’ll have your viaspans, your viaspan spacing, relationship set up. You’ll have your layer constraints, as well as the way that you generate your wide level or your power metal, your wide metal. All of that will be taken care of and then automated into your design setup or should be automated into your design setup.
So once you have that, or actually it doesn’t have to be like a requirement, but the other key phase, and this is absolutely critical, is the assembly/floor planning/design partitioning process. So of course we want to assemble the components and get their topological relationship in place, you know, at this point you can start to do early thermal analysis and figure out, you know, if you’re going to have stress issues as well. But then you can also, the other thing, if you’re going to do an automated layout, you need to go into or have a methodology to do layout partitioning. So in these designs we’re talking about, you know, millions of pins and tens of thousands of individual nets. And these need to be classified into either power nets or signal nets,
on the signal nets, maybe have a subclass if you have differential pairs.
But even then you need to go further than that. You need to go and take these classes and put these into a net group. So for instance, the high speed die-die-die interface that’s between the HBM and the SOC, those are going to have signals that are going to be routed differently than your utility signals that are just going from the die bumps to the BGA. So you’re going to have to be able to associate a different recipe to those different net groups.
Chris Cone
So from there, once you have everything set up, you get to do the fun stuff, which if you’re a layout designer, I call it the fun stuff. This is the fan out and the routing part, right? So fan out is critical because when you want to have a fully automated design for the auto routers to work, you’ll have to bring the power up or down from the die pins and the BGA pins into the RDL or the redistribution layers, the routing or the layers where you’re actually doing the routing.
And so when you’re talking about power, you may have a number of different power schemes that you want to use. Typically you can use a region for like a region of power or you can set up as a floodplain or you can use like a new IC striping capability. And so when you fan out, you may want to fan out with geometrical relationships that will support the IC striping or the power mesh that you’re going to create.
And then you also want to have a fan out that’s going to support either the region or the flood capability. Then on the signal side, you want to be able to fan out your signals, observe minimum routing length if you have route routing link targets, and then enable the routers to take that and then complete the design. And the key thing about this is that it should be flexible. You should be able to mix and match what gets routed first.
If you have everything partitioned into net groups, you can sequence everything automatically, but then you can change the order and improve the routing results. So once you have that, you have everything routed, and it’s 100%, you get a nice score on that, and zero opens, then you go into what’s called the end game.
So the end game is to do your final chip finishing, which is to make sure you have your degassing holes in place, know, they’re meeting either stress or the actual degas requirement.
Chris Cone
You’ll need to observe there might be density rules, so you might have to have a dummy metal fill flow, and there might be additional steps you need to do in order to process your design into a GDS or OASIS format.
And then as part of the end game you want to do a final verification. In my recent project we use Calibre and so we automated that step. Then once you have all these phases done, you’ll want to have a design report. And like I said, be able to run a script or be able to start a replay in the evening and in the morning come in and see a report on what needs to be worked on, what you need your team to work on later to get going to improve your project.
John McMillan
Gotcha. You know, those seem to be very distinct phases. What is the impact on different roles, such as a package designer, layout designer, engineer, signal integrity, power integrity analysis, and so forth?
Chris Cone
When it comes to how it impacts your roles, the way I see it is that we want to, it’s critical that we enable package designers, layout designers, SI/PI architects, to be able to work together in a common framework and to maximize what it is they do best. So an example is the HBM protocol.
In HBM, you’ll have, you need like, it needs to support speeds up to 6.4 gigabits per second per second. And so in order to do that, you’ll need guidance from the SI/PI analyst to show the layout designer what needs to be done to create the breakouts, you know, the routing that needs to go from the die-pin field of the HBM to the die-pin field, or out into free space, and the die-pin field of the SoC out into free space, so they can be connected together,
and when you have the breakouts, the SI/PI analyst can go in,
and make a, you know, go through and analyze it, qualify it, and we can have a lot of confidence that you can basically reuse these breakouts throughout the HBM routing and how you be able to do that and meet all of your electrical requirements.
So the thing that’s kind of key to this is that they need to be able to talk to each other, the layout engineer and the SI/PI analyst, but they also need to have like a common automation language. And that’s the way I see it, that you need to be able to
adopt a suitable automation language that’s not going to turn them into code, into programmers. You want them, you want it to meet what they do best, right? And talk at a very high level. But I think the other thing about the whole flow and the changes in the roles that we have is that somebody needs to step up and work as a replay coordinator. So somebody that can grab all these pieces of the design flow and put it together and be able to do, like I said, just
Chris Cone
Start a replay, run it overnight and see the results in the morning.
John McMillan
Gotcha. So what are the key requirements or ingredients of what you described as an automation recipe?
Chris Cone
So the key requirements that I see is that just at a very high level, I just see three kind of attributes that are required. The first one is it needs to be intuitive. So we have all sorts of ways to automate our tools, and there’s all sorts of complex capabilities that our tools provide. But we want to make sure it’s intuitive. When I’m intuitive, I mean human readable language. So if you’re writing code or if you’re providing a command,
You don’t really want to force people to learn positional arguments and secret handshakes in order to run the code. You want to have a command that’s named exactly what you want to do, like fanout design or autoroute design, and then have a number of switch arguments that allow you to modify the parameters of that command.
The other thing is you want to be flexible. If you’re writing a replay system, you don’t want to have these one-shot commands. If you run it, you can only run it once. You can’t reverse. You can’t hit undo. One of the things we all know in this world is that Control-Z is our friend. When we mess up, we can always undo it and then redo it. We need the flexibility to do that. We need the flexibility to change our routing recipes or our routing order.
There’s a number of things that you need to be able to do in order to create these successful replays. And then finally, it needs to be extensible. So you need to be able to add more features. You’re going to take on new projects and do updates and add more functions and features and kind of grow your capability.
John McMillan
Got it. So intuitive, flexible, and extensible. Gotcha. So you’ve worked with companies on automated workflows. What are your main takeaways from that experience?
Chris Cone
I think the way I see it is going back to really enabling team members to do what they do best. So I wouldn’t trust a code developer to go in and do my SI/PI analysis. So why would I trust the SI/PI analyst to go in and develop code? And it doesn’t make sense. It’s a mismatch there. So kind of the other, I guess, paradigm I think of is just impedance matching the skill set
to plug in to the same framework, right? Whether you’re an SI/PI analyst, if you’re a thermal engineer, if you’re a stress, if you’re just the replay coordinator, which is the role that I take on, then we need to kind of match together, all be matched together inside the framework, the same framework. And so that’s, I think that’s kind of the critical thing that we need to do in order to support doing these successful replays.
John McMillan
Cool, sounds great. Thanks, Chris. This has been really insightful informative. Thanks for taking the time to join me today and sharing your knowledge and thoughts on this very important aspect of 3D IC packaging. That’s it for this episode of the 3D IC podcast. To all our listeners and viewers, I hope you found this podcast as interesting and informative as I have. Thanks for joining us today. Also be sure to check out the show notes to learn more about today’s topic.
And don’t forget to follow this podcast playlist on YouTube or your favorite streaming service so you don’t miss the next episode. Thanks again, Chris. Appreciate it.
Chris Cone
Thank you, John.
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