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Accelerate IC design innovation with Siemens: Navigating the future of 3D IC design to manufacturing

March 7, 2025

In the rapidly evolving semiconductor industry, the drive towards miniaturization and the integration of complex functions through advanced packaging and…

By John McMillan
3 MIN READ

A deep dive into HDAP LVS/LVL verification

January 29, 2024

EDA companies are developing tools and workflows to support HDAP (High-density advanced packaging) LVS/LVL verification. Though the data for achieving “signoff-level” confidence is a work in progress, EDA companies are providing tools that can adapt to different levels of data availability and enable HDAP designers to execute HDAP LVS/LVL flows that are both productive and beneficial.

By John McMillan
4 MIN READ

Parasitic extraction technologies: Advanced node and 3D-IC design

January 2, 2024

Advanced nodes and 3D-IC packages require new and enhanced parasitic extraction processes that can resolve a variety of complex parasitic issues in these designs.

By John McMillan
3 MIN READ

System-level, post-layout electrical analysis for high-density advanced packaging (HDAP)

December 18, 2023

HDAP designs like FOWLP need post-layout simulation (analog) and post-layout STA (digital) flows to augment basic physical verification DRC and LVS.

By John McMillan
3 MIN READ
3D heterogeneous integration devices with multiple 3D IC components

The impact of 3d heterogeneous integration on semiconductor device reliability

December 8, 2022

So far in our 3D IC blog series, we’ve discussed front-end design approaches to develop 3D IC-based devices, the importance…

By Heather George
21 MIN READ
Test engineer performing design rule checks manually for 3D IC heterogenous designs

Assembly level layout vs. schematic in 3D IC design verification

November 8, 2022

In our fifth podcast on 3D IC design workflows, we discussed what a 3D IC physical design workflow looks like,…

By Heather George
16 MIN READ
Engineer seated at computer studying physical prototype for early planning of interconnect systems and design verification workflows

Importance of early planning for interconnect verification in 3D IC physical design workflows

October 24, 2022

In our last podcast on 3D IC architecture workflows, we discussed how a system or microarchitectures determine how to partition…

By Heather George
16 MIN READ
3D IC design engineer using gloved hands to inspect and verify components

Front-end architectural verification considerations for 3D IC design

October 11, 2022

So far in our 3D IC blog series, we’ve discussed efforts to create chiplet ecosystems, design workflow changes needed to…

By Heather George
18 MIN READ
IESF 2022

Learn about heterogeneous integration of semiconductors for autonomous driving, electric vehicle, and ADAS systems at the IESF 2022 automotive conference

August 18, 2022

IESF Automotive began 22 years ago and has been a must-attend event for automotive E/E design experts and executives throughout…

By Keith Felton
2 MIN READ