In our , we discussed the models chiplet vendors need to provide System-in-Package (SiP) integrators to facilitate a chiplet-based design ecosystem. Today, we will discuss the current state of 2.5 and 3D SiP design flows and the evolution required to support the design community to develop these 3D IC-based devices.
Comparing 3D IC packaging and traditional semiconductor packaging workflows
Traditional semiconductor package designs include a single application-specific integrated circuit (ASIC) die or a chip put into a package. Other design types may mount a few chips inside a package and connect via an organic interposer or a multi-chip module (MCM).
For chiplets, it’s a bit different. 3D IC designs (2.5 D and 3D) include multiple dies or chiplets integrated into a single package. The difference between 3D IC designs and existing MCMs is that designers create and optimize chiplets specifically for integration into a single package in conjunction with other chiplets.
ASIC design and package design flows for traditional designs use different design tools, models and workflows. Historically, there was little need for tight collaboration between package design teams and the ASIC design team. Design intent changes from a single chip or chips to integrated chiplets into a single package.
Because 3D IC designs require integrating multiple chiplets into a single system, they require much tighter collaboration with the packaging design team and throughout most of the product design cycle, including system design tools, models, and workflows.
The need to integrate ASIC and package design flows
For the past 40 years, Moore’s Law has enabled the integration of larger portions of a system to be integrated into a single chip, referred to as a System on Chip (SoC). Heterogeneous integration enables the decomposition of systems and subsystems into chiplet-based SiP designs.
System designers must be involved early in the design process to make the necessary trade-offs in partitioning the design into the different chips and chiplets. They need continued collaboration with the RTL design architects and package design teams to assess the trade-offs early in the design process. RTL architects design and functionally verify their designs using a hardware description language, SystemVerilog. RTL design verification will require the package design and planning tools to natively support Verilog, a significant change to the traditional package design process.
Workflows that provide early predictive analysis of system and packages is imperative because once the system and package in ASIC design implementation begin, it’s challenging and expensive to go back and make significant micro-architectural changes.
Chiplet-based SoC designs will leverage standard and custom-designed chiplets. Most designs will require at least one custom ASIC or field-programmable gate array (FPGA) to implement the specific product functionality in conjunction with the general-purpose chiplet devices. The custom ASIC or FPGA design needs to interface to the other chiplets, and these interfaces will deploy the appropriate die-to-die interfaces. The IO planning of the ASIC design requires tight collaboration with the package design lead, who’s responsible for planning the system and package design and implementing the detailed die-to-die interconnect, as well as the interposer and package-level interconnect. Because we are melding the package in the SoC design processes, it’s also necessary to have a combined set of packaging in SoC design, verification, analysis, and sign-off and test flows.
EDA tools, workflows and product design teams need significant changes to support 3D IC integration and packaging
Considering all the above areas, these aren’t minor revisions to today’s workflows. It’s a revolutionary change. The good news is that for 2.5D and even stacked die-type 3D designs, most of the tools exist today. The changes required are to develop the interfaces between tools and scripted workflows and the support for the proposed models or chiplet design kits proposed by the CDX working group.
“True 3D” is a different story and likely years down the road. The general packaging manufacturing technology exists today, but the tools are a work in progress in need of 3D place-and-route [LB(SSIGGI1] algorithms used by very few advanced companies in almost an R&D environment
For 3D design, the stacked die will require new planning in place and route algorithms. Adopting RTL-based design flows for the 2.5 and stacked die type of applications will require package planning tools to support Verilog.
Areas that 3D IC would require new support:
- Verilog support in packaging to capture and validate the correct design intent
- Timing analysis and validation for both high-speed die-to-die interfaces and lower-speed day-to-day interfaces
- Thermal analysis of multiple chiplets with different thermal and power profiles as well as the thermal interaction between different components in a package
- Thermal mechanical stress analysis for thermal coefficients in different substrates
- Design for test (DFT) tools and methodologies adoption
Planning for the new design process for “true” 3D IC will help speed the adoption and prepare design teams for success.
Want to learn more about the impact of 3D IC to design flows? Listen to the podcast now, available on your favorite podcast platform.
View the episode transcript
[00:10] John McMillian: Welcome to the Siemens EDA podcast series on 3D IC Chiplet Ecosystems brought to you by the Siemens Thought Leadership team. In our second podcast on 3D IC Chiplet Ecosystems, we talked about the models that chiplet vendors need to provide to System-in-Package (SiP) integrators to facilitate a chiplet-based design ecosystem. Today, we will discuss the current state of 2.5 and 3D SiP design flows and the evolution required to support the design community to develop these 3D IC-based devices. I’m pleased once again to introduce my special guest, Tony Mastroianni, who is the Director of Advanced Packaging Solutions at Siemens Digital EDA. Welcome back, Tony, thank you for taking the time to talk with me today about 3D IC workflows. And before we dive into the discussion, would you mind giving our listeners just a brief description of your current role and background?
[01:00] Tony Mastroianni: Yes, John, thanks for the introduction. Again, my name is Tony Mastroianni, and I am responsible for developing the two-and-a-half and 3D IC strategies and workflows at Siemens EDA. My background, prior to Siemens, is primarily in the area of IC Design and Project Management. I was involved in developing advanced packaging flows at my previous employer, which was a fabless semiconductor. I’ve been with Siemens for a little over a year now.
[01:35] John McMillian: So Tony, what is it about 3D IC that requires different workflows compared to traditional semiconductor packaging?
[01:43] Tony Mastroianni: Let’s start with a traditional semiconductor package. So, these designs include a single ASIC die or a chip that’s put into a package. Now there are other types of designs that may mount a few chips inside a package, and they’re connected on an organic interposer, which is commonly referred to as a Multi-Chip Module or an MCM. And that technology has been around for many years, these MCMs. When we’re talking about chiplets, it’s a little bit different. For 3D IC designs – which again include two-and-a-half D or 3D – we are including multiple dies or chiplets integrated into the single package. The difference here being the chiplets are specifically designed and optimized for integration into a single package in conjunction with other chiplets. That’s really the difference between an MCM and a 3D IC type of design. So the ASIC design and package design flows for traditional designs use very different design tools and models and workflows. And historically, there has not been a need to have a lot of tight collaboration between the package design teams and the ASIC design teams. So it’s been largely an over-the-wall type of design process. Integrating multiple chiplets into a single system and package design does require a much tighter collaboration: the package, ASIC; and even the system design tools, models, and workflows; as well as tight collaboration throughout most of the product design cycle.
[03:26] John McMillian: So, what, specifically, is driving the need for the integration of these systems: ASIC and package design flows?
[03:33] Tony Mastroianni: For the past 40 years or so, Moore’s Law has enabled the integration of larger portions of a system to be integrated into a single chip, referred to as an SoC or System on Chip. Heterogeneous integration is enabling the decomposition of systems and subsystems into chiplet-based system and package or SiP designs. As such, system designers need to be involved early in the design process to make the necessary trade-offs in partitioning the design into the different chips and chiplets. They will need to collaborate with the RTL design architects and package design teams to assess the trade-offs early in the design process. RTL architects design and functionally verify their designs using a hardware description language, namely SystemVerilog. This will require the package design and planning tools to natively support Verilog, which is a major change to the traditional package design process. Having workflows that can provide early predictive analysis of system and packages is imperative, as once the system and package in ASIC design implementation begin, it’s very difficult and expensive to go back and make major micro-architectural changes. Chiplet-based SoC designs will leverage standard and/or custom design chiplets. But most designs will require at least one custom ASIC – or possibly an FPGA – to implement the specific product functionality in conjunction with the general-purpose chiplet devices. This custom ASIC or FPGA design will need to interface to the other chiplets, and these interfaces will deploy the appropriate die-to-die interfaces. The IO planning of the ASIC design requires tight collaboration with the package design lead who’s responsible for floor planning the system and package design and implementing the detailed die-to-die interconnect, as well as the interposer and package-level interconnect. Furthermore, since we are melding the package in SoC design processes, it’s also necessary to have a combined set of package in SoC design, verification, analysis, and sign-off and test flows.
[05:55] John McMillian: This sounds like a revolutionary change required for the EDA tools, workflows, and product design teams. What are the workflows you envision for 3D IC?
[06:06] Tony Mastroianni: Yes, John, it is indeed a revolutionary change. The good news is that for two-and-a-half D and even stacked die-type 3D designs, most of the tools exist today. Primary change is required for the development of the interfaces between these tools and scripted workflows, as well as the support for the proposed models or chiplet design kits that were proposed from the CDX working group. True 3d is a different story. And true 3D is where you’re actually designing two custom chips and stacking those on top of each other. So, today, those chips – the general packaging manufacturing technology exist today for these types of true 3D stacking. But the tools are really a work-in-progress, so it does require, essentially, 3D place and route algorithms. Those tools are actively in development, but they’re not really commercially available at this point for production-type designs. So, these designs are currently being implemented by very few advanced companies that, again, need very extensive IC design experience. So, they’re currently in more of an R&D type of environment, but it is coming down the road. So, the broad adoption of true 3D will likely be several years away. So, these workflows that we’re talking about include RTL design support, system and package level planning, analysis, physical implementation, verification, and test.
[07:45] John McMillian: You said most of these new workflows can be built with existing tools, what new tools are required? And do any of the tools require incremental functionality?
[07:55] Tony Mastroianni: Clearly, 3D design or true 3D design, the stacked die will require a significant new floor planning in place and route algorithms. The adoption of RTL-based design flows for the two-and-a-half D and stacked die type of applications will require package planning tools to support Verilog. So, this is kind of a new introduction – Verilog support – in the packaging world in order to capture and validate the correct design intent. So, timing analysis and validation will require the traditional packaging or board-level type of signal integrity analysis for the high-speed die-to-die interfaces. Additionally, though, for the lower-speed interfaces, static timing analysis, which is a technology that’s used in the ASIC world will be required for these lower-speed day-to-day interfaces. So, this will require enhancements to the tools that extract the parasitics of these die-to-die interconnects and create the necessary netlist to support either the signal integrity or static timing analysis to include the effects inside the package between the chiplets, the chips, the interposers, and the substrates. Thermal analysis is another area, and this was historically done by the package design or outsourced to OSATs, commonly.
[09:24] Tony Mastroianni: So, this was adequate for traditional homogeneous type of basic designs. But having multiple chiplets – each generating different thermal and power profiles – will require significantly more design-specific analysis, and it’ll be an integral part of the design process. So, although these tools exist, we will require more advanced tools to actually work down at the transistor level, as well as the analysis being introduced as part of the design process to look at the thermal interaction between the different components in the package. So that is a change from what has been done historically for homogeneous designs. Now, since silicone interposers and organic substrates have different thermal coefficients, the thermal expansion and contraction during the manufacturing process, as well as thermal cycling, while an operation can create mechanical defects, and/or reliability concerns with with the interconnect between the substrate and the interposer. So, this is driving the need for thermal mechanical stress analysis tools for two-and-a-half D designs as well as 3D designs for stacked die. So, the day-to-day interconnect for stacked die applications would also require this thermal mechanical stress analysis. And lastly, the integration of multiple chips into a single package does require the adoption of advanced Design For Test, or DFT, tools and methodologies, as well as tighter collaboration with the package design team, and the test, and DFT teams.
[11:11] John McMillian: Which of these 3D IC workflows, is or are, the most critical and why?
[11:16] Tony Mastroianni: So, validation of the design intent would include logical equivalently checking as well as LVS, Layout Versus Schematic. And it’s imperative that the system and package functionality and connectivity defined and verified by the system RTL design teams is actually captured and validated throughout the planning and design implementation process. So, this is really new, these are existing tools that come from the ASIC world but they now are going to be required to be adapted to work in the packaging world. Another important consideration is your power design network within the package, as well as the power integrity analysis. So, by having multiple chips and chiplets inside the package, it does require accurate power analysis to make the necessary design of that power network and validate that each of the components is being receiving the the adequate power and meeting these specification requirements for each of those chiplet components within the package. So, thermal and mechanical stress analysis, 3D IC applications have much more complex thermal and mechanical reliability needs over the homogeneous type of designs. And again, we’ve talked about testing multiple devices in the package; so, this is going to require functional as well as high-speed testing of the die-to-die interfaces. So this is something that’s really not applicable for homogeneous design. But there’s also a need to actually perform the detailed manufacturing tests for each of the chiplets as well within the package. Now, this will require the advanced DFT tools and tighter collaboration, again, between the DFT and test teams and the package design teams to be able to support the testing of these components once the package is assembled. And perhaps one of the most challenging needs will be to deploy security agents and trustability for each of these chiplets, as well as the integration in the design process of the system at the ASIC and package level. So, this is a new requirement, which is still very early in its development process, but it is likely going to be a requirement certainly for [13:48 inaudible] type of applications as well as commercial applications.
[13:53] John McMillian: Great, Tony. Thank you, again, for this yet another highly-informative discussion on chiplet ecosystems in this third episode of our 3D IC series. We’re all at a time for now, but we are looking forward to future podcasts with you on the evolution of the 3D IC workflows. And we want to thank all of our listeners for joining us today.
[14:14] Tony Mastroianni: Yes, thank you all, and thank you, John.