A chip manufacturing line.

Streamlining AI device design using AI and Innovator3D IC Integrator

Two such STCO-related activities are now AI-powered in Innovator3D IC Integrator as part of the 2604 release and deliver superior results in an efficient predictable manner.

3d ic package design

HBM3e and HBM4: IC design guide for next-generation high bandwidth memory 

HBM3e (High Bandwidth Memory) is the current production-grade high bandwidth memory architecture, delivering over 1.2 TB/s per stack and powering the AI…

Abstract visual showing Interconnected data

Data, data, everywhere: Where did it come from, who owns it and is it the right version?

Knowing what is in your IC package design, where it came from, and who touched it last and when, is key to being able to verify with complete certainty and traceability your design’s current status. 

Advanced Thermal Design strategies

Advanced thermal design strategies for 3D IC systems 

Not long ago, OpenAI CEO Sam Altman remarked that advanced AI video generation workloads were pushing GPUs toward their thermal limits….

Screen shot of the Innovator3D IC canvas

The smart path to STCO with Hierarchical Device Planning (HDP)

Siemens partnered with Intel Foundry to develop a STCO centric capability that enables a “smart path” to homogeneous disaggregation using Hierarchical Device Planning and parameterized pin regions.

Co-packaged optics chip

Five Key Trends of Co-Packaged Optics (CPO) in 2026

For years, data-center performance scaled by following a familiar playbook: faster GPUs, higher SerDes rates, and increasingly aggressive board designs….

Six IC packaging trends

Six Key Trends Redefining 3D IC Packaging in the AI Era

Some say we are officially in the Post-Moore’s Law world.  Moore himself closed his seminal paper by mentioning the “day…

Screenshot of Innovator3D IC

Verifying your 2.5/3D IC device assembly level netlist

In this blog we will introduce a new way to verify your 2.5/3D IC device assembly level netlist using formal verification that can exhaustively verify all interconnections between the chiplet blocks.

Calibre-3DThermal-for-3D-IC-design

Thermal management in 3D IC: Challenges, modeling and design strategies 

You are likely here because thermal issues have become the primary constraint shaping your 3D IC design decisions. As 3D integration pushes more performance into smaller footprints, thermal…