Data, data, everywhere: Where did it come from, who owns it and is it the right version?
Knowing what is in your design, where it came from, and who touched it last and when, is key to being able to verify with complete certainty and traceability your design’s current status.
The heterogeneous integration of multiple chiplets in a single packaging platform is critical for many high-performance compute segments, such as AI, hyperscalers, high-performance computing, cloud datacenters, neural processors, and even autonomous vehicles. Such designs contain significant design data and design source IP, that are created, imported, modified and revised throughout the design process as it matures from initial concept through to a converged scenario. During this process many different design teams and designers will be involved, often asynchronously. Design objects that form part of the design may be imported/sourced from 3rd parties or other design teams, such as chiplet LEF/DEF definitions, Verilog netlists, GDSII/OASIS images and many more. It can quickly become a logical nightmare to track and trace, what came from where and when and what version of it is currently being used and who lasted touched it. Without having full visibility/traceability progressing a design to tapeout is a gamble as some design content could be out of date.
What is the solution?
The answer is to use a Work-In-Progress (WiP) data management system to manage all the design and design IP data, revision control every piece of data, record its origin and who last touched it. Now WiP is NOT Product-Lifecycle-Management (PLM) WiP is used during design to ensure that the right data is in the design and provides transparent traceability on where that data came from, when and who last touched/edited it. It can also provide access rights to data and the various levels of a at multiple levels of granularity, such as ecosystem partners such as suppliers, OSATs or foundries, designers or design teams, geographic locations etc.
Enable collaboration
Semiconductor package design requires co-design of multiple concurrent sub-design elements such as dies, interposers, bridges, packages, PCB – each element may be designed in different tools and/or different geos yet require access to common source data. ECO’s can come from customer and must waterfall to each element being designed with each design team. ECO’s often occur when changes in one design element forces changes in other sub-designs of the package. Example: A change in Die bump position requires changes to interposer and the Si bridge design elements.
With Innovator3D IC Data Management (i3DDM) you can set, pull and track ECO/design status across each sub-design to help manage/tracking status of the final semiconductor package design so signoff is a reliable and robust process.
For more information on i3DDM download the brochure that can be found here:
