Semiconductor Packaging

Monolithic scaling limitations drive the growth of 2.5/3D multi-chiplet, heterogeneous integration that enables PPA targets to be met. Our integrated flow addresses prototyping challenges to signoff for FOWLP, 2.5/3D IC, and other emerging integration technologies.

Learn more about semiconductor packaging design and verification.

Latest posts

Streamlining AI device design using AI and Innovator3D IC Integrator

April 27, 2026

Two such STCO-related activities are now AI-powered in Innovator3D IC Integrator as part of the 2604 release and deliver superior results in an efficient predictable manner.

By Keith Felton

2 MIN READ

What’s new in Innovator3D IC 2604

April 27, 2026

This latest Innovator3D IC release brings a raft of design capability and productivity enhancements to the product family, further enabling its ability to design for the latest AI and Hyperscaler devices using advanced heterogeneous integration platforms.

By Keith Felton

2 MIN READ

HBM3e and HBM4: IC design guide for next-generation high bandwidth memory

April 24, 2026

HBM3e (High Bandwidth Memory) is the current production-grade high bandwidth memory architecture, delivering over 1.2 TB/s per stack and powering the AI…

By Emily Yan

8 MIN READ

Streamlining 3D IC design with multiphysics

April 14, 2026

As 3D IC systems continue to scale in complexity, multiphysics is no longer a specialized late-stage activity. It is becoming a core requirement for building designs that can be manufactured successfully and meet long-term performance and lifetime targets.

By Keith Felton

2 MIN READ

Abstract visual showing Interconnected data

Data, data, everywhere: Where did it come from, who owns it and is it the right version?

March 10, 2026

Knowing what is in your IC package design, where it came from, and who touched it last and when, is key to being able to verify with complete certainty and traceability your design’s current status.

By Keith Felton

2 MIN READ

Advanced thermal design strategies for 3D IC systems

February 27, 2026

Not long ago, OpenAI CEO Sam Altman remarked that advanced AI video generation workloads were pushing GPUs toward their thermal limits….

By Emily Yan

6 MIN READ

Screen shot of the Innovator3D IC canvas

The smart path to STCO with Hierarchical Device Planning (HDP)

February 20, 2026

Siemens partnered with Intel Foundry to develop a STCO centric capability that enables a “smart path” to homogeneous disaggregation using Hierarchical Device Planning and parameterized pin regions.

By Keith Felton

2 MIN READ

Five Key Trends of Co-Packaged Optics (CPO) in 2026

February 5, 2026

For years, data-center performance scaled by following a familiar playbook: faster GPUs, higher SerDes rates, and increasingly aggressive board designs….

By Tony Mastroianni

5 MIN READ