Semiconductor Packaging

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Monolithic scaling limitations drive the growth of 2.5/3D multi-chiplet, heterogeneous integration that enables PPA targets to be met. Our integrated flow addresses prototyping challenges to signoff for FOWLP, 2.5/3D IC, and other emerging integration technologies.

Learn more about semiconductor packaging design and verification.

Latest posts

2.5D and 3D IC design testing challenges

Shifting left for earlier testing in 2.5D and3D IC design

March 2, 2023

In our last 3D IC blog, we talked about the impact of 3D IC on device reliability. In today’s blog,…

By Heather George
18 MIN READ
Image of a semiconductor package design

What are the top challenges of high-performance computing/AI semiconductor package design?

February 16, 2023

If you’re designing a high-performance processor-based package,  it’s common for the semiconductor package design to contain multiple logic chips that…

By Keith Felton
3 MIN READ

Revolutionizing semiconductors with 3D IC and chiplet technology

February 9, 2023

Each Industrial Revolution resulted in advancements that propelled humans forward into a seemingly different world. The first in 1784 was…

By Trisha Garrett and Heather George
5 MIN READ
Illustration of a system-in-package (SiP)

How to get your system-in-packages right

January 18, 2023

People have been designing “modules” or system-in-packages (SiP) for a number of years; but in the last 3-5 years, I…

By Keith Felton
2 MIN READ
Illustration that says next generation IC Packaging part 4

The five keys to next-generation IC packaging design: Part 4

December 14, 2022

“Golden signoff” – The final step in the semiconductor packaging process In my last blog post, I talked about the…

By Keith Felton
2 MIN READ
3D heterogeneous integration devices with multiple 3D IC components

The impact of 3d heterogeneous integration on semiconductor device reliability

December 8, 2022

So far in our 3D IC blog series, we’ve discussed front-end design approaches to develop 3D IC-based devices, the importance…

By Heather George
21 MIN READ
Test engineer performing design rule checks manually for 3D IC heterogenous designs

Assembly level layout vs. schematic in 3D IC design verification

November 8, 2022

In our fifth podcast on 3D IC design workflows, we discussed what a 3D IC physical design workflow looks like,…

By Heather George
16 MIN READ

The five keys to next-generation IC packaging design: Part 3

November 3, 2022

Scalability and range of IC packaging design solutions In my last blog, I talked about multi-domain and cross-domain integration that…

By Keith Felton
2 MIN READ
Engineer seated at computer studying physical prototype for early planning of interconnect systems and design verification workflows

Importance of early planning for interconnect verification in 3D IC physical design workflows

October 24, 2022

In our last podcast on 3D IC architecture workflows, we discussed how a system or microarchitectures determine how to partition…

By Heather George
16 MIN READ