Semiconductor Packaging

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Monolithic scaling limitations drive the growth of 2.5/3D multi-chiplet, heterogeneous integration that enables PPA targets to be met. Our integrated flow addresses prototyping challenges to signoff for FOWLP, 2.5/3D IC, and other emerging integration technologies.

Learn more about semiconductor packaging design and verification.

Featured posts

Image showing physical design IP reuse with Xpedition Package designer

Embracing physical design IP reuse as a best practice

July 22, 2024

Efficiency in IC package design is becoming more important as design cycles shorten and complexity surges. One common approach to…

By Keith Felton
2 MIN READ
New innovative way to functionally verify heterogeneous 2D/3D package connectivity

New innovative way to functionally verify heterogeneous 2D/3D package connectivity

June 6, 2024

This blog introduces a white paper that addresses the challenges of verifying
package connectivity and illustrated how to use formal tools to verify connectivity for package designs.

By John McMillan and Todd Burkholder
3 MIN READ
Two people working at a white board with text onscreen that says: Multiplying engineering resources for efficient package substrate design

Multiplying engineering resources for efficient package substrate design

May 14, 2024

In the world of package substrate design, the age-old saying, “many hands make light work,” holds more truth than ever….

By Keith Felton
2 MIN READ

Latest posts

A deep dive into HDAP LVS/LVL verification

January 29, 2024

EDA companies are developing tools and workflows to support HDAP (High-density advanced packaging) LVS/LVL verification. Though the data for achieving “signoff-level” confidence is a work in progress, EDA companies are providing tools that can adapt to different levels of data availability and enable HDAP designers to execute HDAP LVS/LVL flows that are both productive and beneficial.

By John McMillan
4 MIN READ
Siemens 3D IC heterogeneous semiconductor packaging workflows catapult design teams into the future of IC design today.

Workflows for tackling heterogeneous integration of chiplets for 2.5D/3D semiconductor packaging

January 11, 2024

Workflows for tackling heterogeneous integration of chiplets for 2.5D/3D semiconductor packaging.

By John McMillan
4 MIN READ
Image of a chip on a board with text that says Navigating complexities in power delivery analysis: embracing the shift-left approach

Navigating complexities in power delivery analysis: embracing the shift-left approach

January 9, 2024

The demand for increased power and performance in semiconductor packages has surged. As more die and chiplets are integrated into…

By Keith Felton
2 MIN READ

Parasitic extraction technologies: Advanced node and 3D-IC design

January 2, 2024

Advanced nodes and 3D-IC packages require new and enhanced parasitic extraction processes that can resolve a variety of complex parasitic issues in these designs.

By John McMillan
3 MIN READ

Impacts of 3D IC on the future

December 20, 2023

3D IC technology development started many years ago well before the slowing down of Moore’s law benefits became a topic…

By John McMillan
3 MIN READ

System-level, post-layout electrical analysis for high-density advanced packaging (HDAP)

December 18, 2023

HDAP designs like FOWLP need post-layout simulation (analog) and post-layout STA (digital) flows to augment basic physical verification DRC and LVS.

By John McMillan
3 MIN READ

Crossing the chasm: Bringing SoC and package verification together

December 8, 2023

3D IC package designers need assembly-level LVS for HDAP verification.

By John McMillan
2 MIN READ

Package designers need assembly-level LVS for HDAP verification

December 5, 2023

While advanced integrated circuit (IC) packaging is a fast-growing market, comprehensive package verification still has a ways to go. Unique…

By John McMillan
2 MIN READ
An image of an IC package design in Xpedition Package Designer with text that says: Achieving substrate supplier fabrication requirements: a designer's guide

Achieving substrate supplier fabrication requirements: a designer’s guide

December 5, 2023

Designing advanced package layouts with large areas of metal can be a daunting task, given the stringent requirements imposed by…

By Keith Felton
3 MIN READ