Latest Posts

The Five Keys to Next-Generation IC Packaging Design: Part 1

Part 1: An advanced IC packaging design and verification solution For many applications, next generation IC packaging is the best…

3D IC verification requires a golden netlist that allows exceptions

With current 3D IC packaging technologies, since the system-level netlist (the 3D IC design intent) drives system-level LVS verification, designers…

Megatrends of advanced IC packaging solutions 

Over last 2-3 years, everyone has been talking about Moore’s “Law” becoming invalid. Even if it does, we will continue…

IESF 2022

Learn about heterogeneous integration of semiconductors for autonomous driving, electric vehicle, and ADAS systems at the IESF 2022 automotive conference

IESF Automotive began 22 years ago and has been a must-attend event for automotive E/E design experts and executives throughout…

Evolution of 3D IC Architecture and the impact to design flows

Evolution of 3D IC Architecture and the impact to design flows

In our last blog about 3D IC, we discussed the models chiplet vendors need to provide System-in-Package (SiP) integrators to…

3D IC and the system-technology co-optimization (STCO) approach

3D IC and the system-technology co-optimization (STCO) approach

Semiconductor engineers aim to deliver best-in-class devices despite technology scaling and cost limitations of monolithic integrated circuit (IC) design. To…

What’s the current state of 3D IC design?

In the first podcast about 3D IC heterogeneous integration, we talked about the disaggregation of once monolithic implementation architectures into…

Getting your metal fill right

If you’re involved in semiconductor package design using routable substrates — that is, as opposed to leadframe based — then…

The beginner’s guide to 3D IC

The beginner’s guide to 3D IC

As consumer electronic devices grow increasingly connected, intelligent and advanced, designers need new methodologies such as 3D IC to address…