Semiconductor Packaging

Monolithic scaling limitations drive the growth of 2.5/3D multi-chiplet, heterogeneous integration that enables PPA targets to be met. Our integrated flow addresses prototyping challenges to signoff for FOWLP, 2.5/3D IC, and other emerging integration technologies.

Learn more about semiconductor packaging design and verification.

Getting your metal fill right

July 14, 2022

If you’re involved in semiconductor package design using routable substrates — that is, as opposed to leadframe based — then…

By Keith Felton

2 MIN READ

The beginner’s guide to 3D IC

July 7, 2022

As consumer electronic devices grow increasingly connected, intelligent and advanced, designers need new methodologies such as 3D IC to address…

By Heather George

17 MIN READ

Semiconductor package design market trends: 2023 forecast from Siemens EDA

June 29, 2022

Semiconductor package design industry in 2023 expects to see accelerated growth of heterogeneous integration resulting emergence and adoption of new technology.

By Keith Felton

3 MIN READ