Monolithic scaling limitations drive the growth of 2.5/3D multi-chiplet, heterogeneous integration that enables PPA targets to be met. Our integrated flow addresses prototyping challenges to signoff for FOWLP, 2.5/3D IC, and other emerging integration technologies.

Learn more about semiconductor packaging design and verification.

Featured posts

Latest posts

Image of a semiconductor package design

What are the top challenges of high-performance computing/AI semiconductor package design?

If you’re designing a high-performance processor-based package,  it’s common for the semiconductor package design to contain multiple logic chips that…

Revolutionizing semiconductors with 3D IC and chiplet technology

Each Industrial Revolution resulted in advancements that propelled humans forward into a seemingly different world. The first in 1784 was…

Illustration of a system-in-package (SiP)

How to get your system-in-packages right

People have been designing “modules” or system-in-packages (SiP) for a number of years; but in the last 3-5 years, I…

Illustration that says next generation IC Packaging part 4

The five keys to next-generation IC packaging design: Part 4

“Golden signoff” – The final step in the semiconductor packaging process In my last blog post, I talked about the…

3D heterogeneous integration devices with multiple 3D IC components

The impact of 3d heterogeneous integration on semiconductor device reliability

So far in our 3D IC blog series, we’ve discussed front-end design approaches to develop 3D IC-based devices, the importance…

Test engineer performing design rule checks manually for 3D IC heterogenous designs

Assembly level layout vs. schematic in 3D IC design verification

In our fifth podcast on 3D IC design workflows, we discussed what a 3D IC physical design workflow looks like,…

The five keys to next-generation IC packaging design: Part 3

Scalability and range of IC packaging design solutions In my last blog, I talked about multi-domain and cross-domain integration that…

Engineer seated at computer studying physical prototype for early planning of interconnect systems and design verification workflows

Importance of early planning for interconnect verification in 3D IC physical design workflows

In our last podcast on 3D IC architecture workflows, we discussed how a system or microarchitectures determine how to partition…

The five keys to next-generation IC packaging design: Part 2

Multi-domain integration enables faster time to market for complex advanced semiconductor packages with a seamless integration of design and verification.