Semiconductor Packaging

Monolithic scaling limitations drive the growth of 2.5/3D multi-chiplet, heterogeneous integration that enables PPA targets to be met. Our integrated flow addresses prototyping challenges to signoff for FOWLP, 2.5/3D IC, and other emerging integration technologies.

Learn more about semiconductor packaging design and verification.

Latest posts

3D heterogeneous integration devices with multiple 3D IC components

The impact of 3d heterogeneous integration on semiconductor device reliability

December 8, 2022

So far in our 3D IC blog series, we’ve discussed front-end design approaches to develop 3D IC-based devices, the importance…

By Heather George

21 MIN READ

Test engineer performing design rule checks manually for 3D IC heterogenous designs

Assembly level layout vs. schematic in 3D IC design verification

November 8, 2022

In our fifth podcast on 3D IC design workflows, we discussed what a 3D IC physical design workflow looks like,…

By Heather George

16 MIN READ

The five keys to next-generation IC packaging design: Part 3

November 3, 2022

Scalability and range of IC packaging design solutions In my last blog, I talked about multi-domain and cross-domain integration that…

By Keith Felton

2 MIN READ

Engineer seated at computer studying physical prototype for early planning of interconnect systems and design verification workflows

Importance of early planning for interconnect verification in 3D IC physical design workflows

October 24, 2022

In our last podcast on 3D IC architecture workflows, we discussed how a system or microarchitectures determine how to partition…

By Heather George

16 MIN READ

The five keys to next-generation IC packaging design: Part 2

October 19, 2022

Multi-domain integration enables faster time to market for complex advanced semiconductor packages with a seamless integration of design and verification.

By Keith Felton

2 MIN READ