Monolithic scaling limitations drive the growth of 2.5/3D multi-chiplet, heterogeneous integration that enables PPA targets to be met. Our integrated flow addresses prototyping challenges to signoff for FOWLP, 2.5/3D IC, and other emerging integration technologies.

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3D heterogeneous integration devices with multiple 3D IC components

The impact of 3d heterogeneous integration on semiconductor device reliability

So far in our 3D IC blog series, we’ve discussed front-end design approaches to develop 3D IC-based devices, the importance…

Test engineer performing design rule checks manually for 3D IC heterogenous designs

Assembly level layout vs. schematic in 3D IC design verification

In our fifth podcast on 3D IC design workflows, we discussed what a 3D IC physical design workflow looks like,…

The five keys to next-generation IC packaging design: Part 3

Scalability and range of IC packaging design solutions In my last blog, I talked about multi-domain and cross-domain integration that…

Engineer seated at computer studying physical prototype for early planning of interconnect systems and design verification workflows

Importance of early planning for interconnect verification in 3D IC physical design workflows

In our last podcast on 3D IC architecture workflows, we discussed how a system or microarchitectures determine how to partition…

The five keys to next-generation IC packaging design: Part 2

Multi-domain integration enables faster time to market for complex advanced semiconductor packages with a seamless integration of design and verification.

3D IC design engineer using gloved hands to inspect and verify components

Front-end architectural verification considerations for 3D IC design

So far in our 3D IC blog series, we’ve discussed efforts to create chiplet ecosystems, design workflow changes needed to…

what's new in Xpedition IC Packaging

What’s new in Xpedition Advanced IC Packaging release VX.2.12

The Xpedition high density advanced packaging solution it is made up of two core products, Xpedition Substrate Integrator (xSI) which…

The Five Keys to Next-Generation IC Packaging Design: Part 1

Part 1: An advanced IC packaging design and verification solution For many applications, next generation IC packaging is the best…

3D IC verification requires a golden netlist that allows exceptions

With current 3D IC packaging technologies, since the system-level netlist (the 3D IC design intent) drives system-level LVS verification, designers…