Semiconductor Packaging

Filter by:

Monolithic scaling limitations drive the growth of 2.5/3D multi-chiplet, heterogeneous integration that enables PPA targets to be met. Our integrated flow addresses prototyping challenges to signoff for FOWLP, 2.5/3D IC, and other emerging integration technologies.

Learn more about semiconductor packaging design and verification.

Featured posts

Illustration of 3D IC stacked design

3D IC technology: your comprehensive guide to enabling heterogeneous integration

May 19, 2025

What is 3D IC technology? 3D IC technology refers to the integration of multiple silicon dies or wafers in a…

By John McMillan
14 MIN READ
Screen shots of Innovator3D IC software in use.

Exploring TSMC InFO_oS and InFO_PoP certification

February 28, 2025

Siemens EDA has recently achieved this certification for Xpedition Package Designer as part of the TSMC InFO_oS and InFO_PoP workflows.

By Keith Felton
2 MIN READ
Text that says what's new in IC Packaging 2409 next to a stylized X

What’s new in IC Packaging 2409

September 19, 2024

The 2409 release is a landmark update in the field of electronic design automation (EDA), introducing a next-generation solution for…

By Keith Felton
3 MIN READ

Latest posts

Enabling comprehensive DFT for chiplets and 3DICs using Tessent Multi-die

September 24, 2024

Learn about Siemens’ Tessent Multi-die solution for 3DIC packaging.

By John McMillan
4 MIN READ
Text that says what's new in IC Packaging 2409 next to a stylized X

What’s new in IC Packaging 2409

September 19, 2024

The 2409 release is a landmark update in the field of electronic design automation (EDA), introducing a next-generation solution for…

By Keith Felton
3 MIN READ
Image of a 3D IC with text that says TSMC 2024 NA OIP Ecosystem Forum

Join us at the TSMC 2024 NA OIP Ecosystem Forum

September 18, 2024

The TSMC 2024 North America OIP (Open Innovation Platform®) Ecosystem Forum is just around the corner, and Siemens EDA is…

By Keith Felton
3 MIN READ

User2User 2024: Silicon photonics to integrate chiplets: Swissbit

September 17, 2024

Swissbit is pioneering chiplet and system-on-package solutions that embed security and functional safety from the design phase to meet stringent requirements in harsh industrial and automotive environments.

By John McMillan
3 MIN READ
User2User 2024: Chiplets for future automotive application: Fraunhofer

User2User 2024: Chiplets for future automotive application: Fraunhofer

September 11, 2024

Andy Heinig, Head of Department Efficient Electronics at Fraunhofer, explains why automotive is especially a good market and enabler for chiplets and presents different use cases for chiplets that are on the horizon.

By John McMillan
3 MIN READ

The evolution of machine learning (ML) in the physical design and verification of semiconductor packages

August 14, 2024

Discover how Siemens’ EDA evolution of machine learning in the physical design and verification of semiconductor packages.

By John McMillan
2 MIN READ

User2User 2024: EMIB based advanced packaging flow – Intel Foundry

August 12, 2024

Learn how Intel uses 3DIC verification to leverage Siemens XSI & Calibre 3DSTACK for DRC, LVS, assembly checks. Explore methodologies for high-performance systems.

By John McMillan
3 MIN READ

Why is a comprehensive workflow essential for chiplet design and today’s 3D IC architectures?

August 8, 2024

Explore this infographic to learn why a comprehensive workflow essential for chiplet design and today’s 3D IC architectures.

By John McMillan
2 MIN READ

The multi-physics challenge: Known good die may not behave in 3D IC as stand alone!

August 5, 2024

Discover how Siemens’ EDA tackles the multi-physics challenge to achieve fast, accurate assembly-level physical verification.

By John McMillan
2 MIN READ