Monolithic scaling limitations drive the growth of 2.5/3D multi-chiplet, heterogeneous integration that enables PPA targets to be met. Our integrated flow addresses prototyping challenges to signoff for FOWLP, 2.5/3D IC, and other emerging integration technologies.

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Image of an IC package design with text that says A workflow methodology for homogeneous disaggregation using hierarchical device planning

A workflow methodology for homogeneous disaggregation using hierarchical device planning

Advancements in IC packaging manufacturing, combined with the exploding costs of designing monolithic ICs on today’s advanced process nodes, have…

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A “big rock” approach to DC drop analysis in IC package design

The key analysis needs of high-performance computing semiconductor package design Today, power requirements are continually increasing as you bring more…

Illustration of an IC Package design with text that says Why are you spending 30%+ more time on semiconductor packaging design?

Why are you spending 30%+ more time on semiconductor packaging design?

Designs are just getting bigger and more complex Yes, an obvious aspect is increasing design complexity. Packages are now a…

Illustration of 3D IC design workflows

Why co-design-driven semiconductor package planning and prototyping is critical for design success

The connectivity management complexity of package assemblies where multiple chiplets/ASICs and memory are heterogeneously integrated, introduces a great deal of…

An image of a PCB with text that says IC Packaging 2.13

What’s new in Xpedition IC Packaging release VX.2.13

The Xpedition high density advanced packaging solution it is made up of two core products, Xpedition Substrate Integrator (xSI) which…

2.5D and 3D IC design testing challenges

Shifting left for earlier testing in 2.5D and3D IC design

In our last 3D IC blog, we talked about the impact of 3D IC on device reliability. In today’s blog,…

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What are the top challenges of high-performance computing/AI semiconductor package design?

If you’re designing a high-performance processor-based package,  it’s common for the semiconductor package design to contain multiple logic chips that…

Revolutionizing semiconductors with 3D IC and chiplet technology

Each Industrial Revolution resulted in advancements that propelled humans forward into a seemingly different world. The first in 1784 was…

Illustration of a system-in-package (SiP)

How to get your system-in-packages right

People have been designing “modules” or system-in-packages (SiP) for a number of years; but in the last 3-5 years, I…