Semiconductor Packaging

Filter by:

Monolithic scaling limitations drive the growth of 2.5/3D multi-chiplet, heterogeneous integration that enables PPA targets to be met. Our integrated flow addresses prototyping challenges to signoff for FOWLP, 2.5/3D IC, and other emerging integration technologies.

Learn more about semiconductor packaging design and verification.

Featured posts

Text that says what's new in IC Packaging 2409 next to a stylized X

What’s new in IC Packaging 2409

September 19, 2024

The 2409 release is a landmark update in the field of electronic design automation (EDA), introducing a next-generation solution for…

By Keith Felton
3 MIN READ

Siemens introduces Innovator3D IC – a comprehensive multiphysics cockpit for 3D IC design, verification and manufacturing

July 31, 2024

Innovator3D IC – a comprehensive multiphysics cockpit for 3D IC design, verification and manufacturing

By John McMillan
4 MIN READ
Image showing physical design IP reuse with Xpedition Package designer

Embracing physical design IP reuse as a best practice

July 22, 2024

Efficiency in IC package design is becoming more important as design cycles shorten and complexity surges. One common approach to…

By Keith Felton
2 MIN READ

Latest posts

SemiWiki Podcast – An expert panel discussion on the move to chiplets

September 13, 2023

Listen in as Tony Mastroianni Advanced Packaging Solutions Director – Siemens EDA along with Saif Alam Vice President of Engineering…

By John McMillan
< 1 MIN READ
system technology co-optimization

Shifting left with system technology co-optimization for IC packaging

August 17, 2023

We have witnessed and learned about the industry’s significant shift in semiconductors. The traditional approach of transistor scaling, once universally…

By Keith Felton
3 MIN READ
Image of an IC package design with text that says A workflow methodology for homogeneous disaggregation using hierarchical device planning

A workflow methodology for homogeneous disaggregation using hierarchical device planning

July 20, 2023

Advancements in IC packaging manufacturing, combined with the exploding costs of designing monolithic ICs on today’s advanced process nodes, have…

By Chris Cone
5 MIN READ
Image of a boulder in a desert

A “big rock” approach to DC drop analysis in IC package design

June 15, 2023

The key analysis needs of high-performance computing semiconductor package design Today, power requirements are continually increasing as you bring more…

By Steve McKinney
4 MIN READ
Illustration of an IC Package design with text that says Why are you spending 30%+ more time on semiconductor packaging design?

Why are you spending 30%+ more time on semiconductor packaging design?

May 18, 2023

Designs are just getting bigger and more complex Yes, an obvious aspect is increasing design complexity. Packages are now a…

By Keith Felton
2 MIN READ
Illustration of 3D IC design workflows

Why co-design-driven semiconductor package planning and prototyping is critical for design success

April 20, 2023

The connectivity management complexity of package assemblies where multiple chiplets/ASICs and memory are heterogeneously integrated, introduces a great deal of…

By Keith Felton
3 MIN READ
An image of a PCB with text that says IC Packaging 2.13

What’s new in Xpedition IC Packaging release VX.2.13

March 15, 2023

The Xpedition high density advanced packaging solution it is made up of two core products, Xpedition Substrate Integrator (xSI) which…

By Keith Felton
2 MIN READ
2.5D and 3D IC design testing challenges

Shifting left for earlier testing in 2.5D and3D IC design

March 2, 2023

In our last 3D IC blog, we talked about the impact of 3D IC on device reliability. In today’s blog,…

By Heather George
18 MIN READ
Image of a semiconductor package design

What are the top challenges of high-performance computing/AI semiconductor package design?

February 16, 2023

If you’re designing a high-performance processor-based package,  it’s common for the semiconductor package design to contain multiple logic chips that…

By Keith Felton
3 MIN READ