The connectivity management complexity of package assemblies where multiple chiplets/ASICs and memory are heterogeneously integrated, introduces a great deal of anxiety and uncertainty, making it a focal point for many engineering teams. Fortunately, regardless of substrate or interconnect technology, leading-edge companies are adopting early planning and prototyping of their complex heterogeneously integrated devices and using co-design to optimize across the entire device/system assembly that is known as System Technology Co-Optimization or STCO.
The problem: disparate data sources
One of the first challenges with 2.5D or 3D heterogeneously integrated designs is the disparate format of data sources. With the emergence of chiplet solutions, this problem will become even more of an issue as data from multiple sources is unlikely to be available in a single common format.
For example, a chiplet provider will deliver a GDS representation of the chiplet along with an Excel ball map. The silicon design is written in Verilog. The physical device uses a mixture of LEF/DEF, GDS, and CSV files. And the BGA package comes in ODB++.
How do designers bring this variety of data and formats together into something they can use to manage their design’s connectivity? And how do they do this without reimplementing, redesigning, or recapturing design elements from their native format? This would break the digital-thread and potentially result in a flawed digital-model or twin of the device.
The solution: aggregate the data formats
Substrate design teams need a solution that can quickly and accurately aggregate many data formats into a single cohesive system representation and netlist. In other words, they need a connectivity management solution that can consume data from the various sources and formats and present it to them intelligently. Once the source data has been imported into the connectivity management tool, the various pieces can be exported to the appropriate implementation tool, so they can address analysis problems such as thermal, signal integrity, power integrity, IR drop, system level LVS, assembly checking, and more.
For example, in a typical 2.5D interposer package design, the interposer can be exported to a place-and-route tool and the package exported to a package design tool. If the design changes, the full system is updated, and new data is sent out for implementation.
By leveraging a “golden” netlist of the system ensures that the various parts of the system stay in sync and provides a platform to validate the implementation against the netlist from a full-system perspective – utilizing a system-level layout versus schematic (LVS) verification workflow.
The same principle applies to the interconnects
For planning purposes, the interconnects between the various devices are important. This includes the physical representation of the various chiplets or dies involved, along with the platform these devices will sit on. There are tools for each of these disciplines, and just as with the variety of design data sources, they each have their own format. The silicon team uses a set of place-and-route tools or a custom layout tool to design the die. The interposer design team needs to know what the interface looks like between the die and the rest of the system, both from a netlist perspective – what’s connected to what – and in relation to the physical bump layout. This information can be shared in any number of formats. Industry standards used include LEF/DEF, GDS, and often simple XY reports in Excel or some other CSV file.
The challenge is, when things change, how does each tool get updated? Formats like LEF/DEF can be passed back and forth between the interposer planning tool and the silicon tool as well as between the package planning tool and the silicon tool. Yet, there will also be input from the board team. Often a PCB design influences the package design. However, there is not an industry standard interchange format between the board, the package, and the interposer teams.
Fortunately, ODB++ is an excellent interchange format for bringing in PCB data or package data into the planning environment to support collaboration and optimization. This enables designers to make trade-off decisions for both the package and the board and communicate those recommendations back to the other design team in formats that are native to their tools.
For example, during package planning designer can utilize co-design-driven semiconductor package planning techniques to move bumps around to make the package design simpler, and then pass the proposed bump changes back to the silicon team via DEF files. If the ASIC team accept the changes, they become part of the solution moving forward.
Using co-design-driven semiconductor package planning to optimize across the entire device/system assembly
By supporting different design and vendor tools, a true connectivity management and package assembly planning and co-design solution enables designers and design teams to use the implementation solution appropriate to their target technology.
Learn about co-design-driven semiconductor package planning and the 3D IC design workflows available to designers in our eBook: Semiconductor packaging: making the right connections in 3D IC design.