Advancements in IC packaging manufacturing, combined with the exploding costs of designing monolithic ICs on today’s advanced process nodes, have given rise to a growing trend of disaggregating large SoCs into smaller dies and chiplets. This increased design complexity requires iterative multi-physics analysis during the floorplanning stage and optimization of the design for PPA and cost goals, significantly raising the barrier for project success. Trying to employ traditional package design solutions – where each device is modeled as a single flat entity – is time consuming and unnecessarily risks delaying production.
In this blog I will present a workflow methodology for homogeneous disaggregation using hierarchical device planning. The key benefit of adopting hierarchy inside of a design is clear – a seemingly large and complex designs can be disaggregated into smaller and easier to manage building blocks based on a collection of attributes such as function and position. Yet we also need to consider that many design structures are comprised of repeatable patterns that can be represented as a parameterized object which is a form of hierarchical design capture. In IC packaging there are two key classes of design structures which lend easily to incorporating hierarchy – these are die-to-die signal interfaces and power distribution networks.
Die-to-die signal interfaces
Die-to-die signal interfaces are normally implemented as uniform signal bump collections placed at least twice in the system – once in each of the die that are being interfaced. Let’s take a standard JESD235B HBM Ballout A footprint as an example. The HBM interface is comprised of repeating channels which simplifies routing and post-layout analysis process at the interface level. Similarly, preserving this die-to-die interface as a hierarchical block in the IC package floorplan significantly reduces the layout routing and post-layout analysis cycle time the system level.
An example scenario of the use of hierarchical device planning
Let’s say we have a BGA that 15mm by 15mm using 30 μm diameter ball-maps on a 50 μm pitch. It is hierarchically constructed using 4 levels of hierarchy and has almost 15,000 unique net connections at the top level including global VDD and VSS signals. The primary building block of the design next to the top-level design is a 250 μm X 250 μm footprint to enable it to be automatically arrayed in both the x and y direction. As system-wide power and ground distribution is a key function of this building block, it will require frequent changes through the design process. The hierarchical design is created in Xpedition Substrate Integrator (xSI), with each level of the hierarchical created within the floorplan design context and then exported into a single part entity that can be referenced in a new floorplan design representing a higher level of hierarchy.
Each of the building blocks will receive a topological pin region which is used to define the connectivity as it is placed in higher levels of hierarchy. The device representation of building blocks in xSI allows designers to add a topological pin region to define key attributes of the pins including the connectivity as it is placed in higher levels of hierarchy. This allows designers to define formulas for deriving the connectivity attributes of the block using regular expressions along with several available design attribute tokens. Derived connectivity can then be automatically regenerated after design modifications and can be driven using automation.
To explain the detailed design iteration process, level 0 device will be modified to change the power and ground hexagonal layout to go in the horizonal direction instead of vertical and to add a new signal “Sense” which will be propagated up the hierarchy. At the floorplan where the device is placed, the designer exports it into a single part while specifying the “functional signal creation” to “use net names” mapping. Once the part at the lower level is exported, it can be imported into a higher-level floorplan using the import part form. Here the designer can specify the path to the part along with the reference designator, the master cell name, and the instance name. Once the block at the lower level is exported, it can be imported into the higher-level floorplan. In this design example, the number of unique nets increased from 14962 to 17362 indicating that 2400 new unique derivations of the net “Sense” were created.
Power distribution networks
Power distribution networks are typically implemented in several geometric regions of the system design with a bump assignment scheme applied to meet a specific physical routing implementation such as checker-board bump pattern for a two-layer power ground mesh.
The primary power/ground domain in a typical silicon interposer – while requiring pin counts easily exceeding 100,000 bumps – are surprisingly simple. The region will have a specific pin pattern, pad stack definition, and a repeating signal assignment pattern (checkerboard or horizontal/vertical striped). A highly efficient way to represent this design structure is as a set of parameterized pin regions.
Besides defining the pin placement geometry, the pin region contains a set of parameterized attributes to specify the desired 30 μm diameter pad stack using an orthogonal pattern with a 50 μm pitch and 50 μm pin to region boundary setting. When ready, the IC package designer can simply select these two regions and regenerate the pins to flood the encapsulated areas. Following this, the designer creates the automated VDD/VSS signal assignments in a checker-board pattern. After the pins are generated for the core design level, it can be exported as a part and imported into the full SoC soft IP level and then exported as a part for system assembly as well as exported as a LEF model for IC design implementation.
Rearchitecting your SoC into chiplets
When a design is constructed using hierarchical building blocks to represent the die-to-die interfaces along with parameterized pins to represent power distribution networks and signal patterns, the path to rearchitecting your SoC into chiplets is clear. Starting with the soft IP SoC representation, after the pins are removed, the region geometries can be quickly modified into a chiplet configuration. Using the same process, the pins are generated and numbered with corresponding derived signal sets. The pins in each of the four quadrants can be collectively selected and exported as a part to create a placeable building block for each chiplet.
Die-to-die interface for the HBM
The key interface architecture between chiplets, die and HBM memory is the die-to-die building block protocol. These can include custom interfaces as well as standard interfaces such as HBM (JEDEC) or the Universal Chiplet Interconnect Express (UCIe). To intuitively manage the connective of several interfaces, the HBM and D2D interfaces are covered by pin regions with an attribute to prefix each of the connected nets with the instance name of the building block to define a unique interface connection. After this is done, it can be exported as a full chiplet part to be brought into the top-level floorplan as well as exported as a LEF block for co-optimization using your preferred IC place and route tools such as Aprisa. Once you have a complete prototype that meets expectation you can then move into detailed implementation without the risk of significant ECO’s.
To dive deeper into this topic download: The smart path to chiplets using hierarchical device planning and pin regions.