What’s new in Xpedition IC Packaging release VX.2.13

By Keith Felton

The Xpedition high density advanced packaging solution it is made up of two core products, Xpedition Substrate Integrator (xSI) which is for constructing and optimizing complete package assemblies, which can include multiple ASIC, chiplets, discretes, interposers, packages, and even PCBs. Then there is Xpedition Package Designer (xPD), this is the detailed physical place and route tool, the packaging version of Xpedition Layout. xPD contains two other technologies, the first is HyperLynx DRC the second is HyperLynx FAST3D quasi-static field solver.

xSI is the data aggregator and performs initial placement of devices with bump/ball logic assignment and optimization. It supports and ECO flow with IC design tools to enable silicon-package co-design. It then feeds the optimized prototype into xPD for detailed physical implementation. This platform integrates with and leverages a very broad portfolio of Siemens technologies to achieve comprehensive verification all the way down to thermal analysis and thermally induced mechanical stress.

The new VX.2.13 release of Xpedition IC Packaging addresses the increasing complexity of today’s IC Packaging needs through multiple areas that span xSI and xPD.

Custom user layers with drawing & annotation

Enables designers to draw and annotate on custom layers at each level of package hierarchy and export the information for predictive analysis. The drawing function supports the ability to draw text, lines, closed polygons, rectangles and circles and is commonly used for the creation of thermal heat spreaders and substrate stiffeners.

Conductive metal planes import

Designers can now Import plane shapes, conductive shapes and teardrops from xPD/xPCB designs. This allows for better planning tradeoffs and allows for more accurate early analysis as the metal planes/shapes can be exported for SI/PI

Hierarchical Device Planning with “smart regions”

“Smart Regions” enables rapid hierarchical prototyping of complex ASICs and chiplets. The “Smart Regions” are parametric regions that can auto synthesize arrays of pins or LEF macros and region anchoring provides automatic region move when a region is resized.

Complex via array reuse

Reduces design time and potential errors through the ability to reuse design IP within a design and across designs and teams. Minimizes time needed to re-create complex vias in similar designs and promotes usage of known good via arrays

Improved performance on very large designs

Improved deign load performance on very large designs by up to 18% and improved interactive performance on designs with large plane nets ranging from 17% to 100%. This helps reduce design cycle times and improved designer productivity.

Teardrop support for pads at route T-junctions

Tear drops can now be automatically created/added to pads or vias located at route T-junctions​. This improves signal performance and substrate manufacturing yield.

The new VX.2.13 release of Xpedition IC Packaging

Overall VX2.13 delivers considerable value across xSI and xPD. To learn more and watch a series of demo videos, visit the what’s new in Xpedition IC Packaging VX.2.13 release page.

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This article first appeared on the Siemens Digital Industries Software blog at