“Golden signoff” – The final step in the semiconductor packaging process
In my last blog post, I talked about the scalability and range of your design solution that is required to tackle current and future advanced semiconductor packages, and what is required for predictable precision manufacturing handoff. This blog will discuss methods and best-practices test capabilities so designers can attain golden signoff more efficiently and quickly.
Golden signoff in semiconductor packaging
Now, you’re probably thinking to yourself, “What does he mean by golden signoff?” Well, the term “golden signoff” refers to when designers use their foundry or outsourced semiconductor assembly and test (OSAT) providers approved signoff design rule checking (DRC) tools and the supplied PDK/PADKs, as well as other signoff documentation, such as a design rule manual (DRM).
This generally achieves only fabrication signoff for the substrates being fabricated (interposer, package). For advanced semiconductor packages where multiple ASICs and/or chiplets are being heterogeneously integrated, golden signoff requires a much more comprehensive set of checks; otherwise, the final completely assembled devices yield may not hit expected targets and will result in an overrun of the projected and expected assembly and test costs.
Shift-left approach – A solution for advanced semiconductor packaging
Comprehensive golden signoff should include, as a minimum: physical verification, connectivity checking (aka, LVS), and heterogeneous assembly-level verification (aka, LVL). Such a comprehensive signoff checking process can highlight many issues that require re-work. If not detected, these issues can easily delay projects, add costs, and lead to missed manufacturing schedules.
One way to prevent this from happening is to implement a “shift-left” design flow, performed in-design to locate and eliminate obvious sign-off errors early. Using such a methodology can remove over 80 percent of sign-off errors and prevent sign-off bottlenecks and delays.
Now ensuring that your advanced semiconductor package can be fabricated and assembled correctly and achieve expected yields is great, but it also must function. That’s why test is so important and cannot be overlooked or left as an afterthought. To start with you need to be using known good die (KGD) but that is not enough, you also need to utilize package-level test by reusing die-level built-in self-test (BIST) and scan patterns mapping them to the package level.
In summary these next generation semiconductor packages require a robust and comprehensive golden signoff.
If you would the read more about this golden signoff process then please download this paper.