We expect to see 2023 bring greater emphasis and focus in several areas of semiconductor package design:
Accelerated growth of heterogeneous integration multiple die/chiplet SiPs
To start with, heterogeneous integration (HI) of multiple die into system-in-packages (SiPs) will be common across all market segments and will use multiple integration platforms, not just silicon interposers, as is common today.
These complex multi-die/chiplet designs will see a greater usage of hardware description language (HDL)-driven flows, which speed system definition and debug cycles compared to today’s schematic-driven approaches.
As these HI multi-die/chiplet SiPs grow and become more complex, the adoption and usage of system-level design rule checking (DRC) and layout verses schematic (LVS) verification will become mandatory in semiconductor package design in order to avoid fabrication and manufacturing assembly issues/errors and their corresponding negative impact on costs and delays.
The emergence and adoption of organic-based interposers
As heterogeneous integration using chiplets start to become common — almost mainstream — so will the emergence of a robust supply chain of commercial off-the-shelf (COTS) chiplets containing what was previously available as soft/hard IP, as used in monolithic SoC designs.
This will lead to the emergence and adoption of alternatives to silicon as an integration substrate in semiconductor package design. Organic-based interposers will deliver the wiring density and electrical/thermal performance needed for many target markets and of course enable larger sizes, due to no reticle limitations and lower costs.
Early detection of thermal and electromechanical issues
As HI grows in adoption and usage and its available integration platforms grow, so will the number of die/chiplet integration permutations. As a result, issues around thermal and electromechanical stress will become pervasive. Engineers will need to address these issues earlier in the planning and prototyping to prevent them from becoming a key problem.
This will mandate and drive the usage of early predictive thermal and stress analysis, in addition to the current early SI/PI analysis. Ideally, this should happen during the planning and prototyping process. This will enable the semiconductor packaging team to identify and qualify acceptable integration scenarios and reject unacceptable scenarios.
The development of a more comprehensive system-level test
The final area we see greater emphasis and focus in 2023 is test.
Reliance on known-good-die or chiplets (KGD) by itself will not be sufficient to ensure functional performance and reliability. These designs will require the adoption and usage of more comprehensive test strategies capable of addressing the new test challenges presented by such 2.5D/3D IC SiP designs. (By “test,” I mean complete system-level test which will include the active and passive devices as well as the integration substrates and any embedded active or passive devices within them.)
In summary, our team at Siemens EDA believes that 2023 will see many areas of semiconductor package design considerably different from today. Some will be completely new; others will have grown or matured in their adoption and usage driven by complexity demands.
In addition, an ecosystem around the supply and standardization of chiplets will have emerged, enabled by exchange formats such as those being created by Open Compute Projects Chiplet Design eXchange (CDX) format, and will provide the driver and catalyst for broad adoption of HI across all market segments, and not just a capability for the current handful of mega IDM’s/fabless and systems companies.