Discover how AI is changing the nature of semiconductor design

AI is shaping the semiconductor industry’s future and its alignment with Siemens’ commitment to innovation and enhancing sustainability by accelerating…

Assembly Verification Flow for Silicon Interposers with Embedded Deep Trench Capacitance

User2User 2024: Assembly verification flow for silicon interposers

In this User2User 2024 session Broadcom’s Suvarna Vikhankar presents “Assembly Verification Flow for Silicon Interposers with Embedded Deep Trench Capacitance”

Advanced Physical Verification Flows for 3DICs

User2User 2024: Advanced physical verification flows for 3D IC’s

In this User2User 2024 video presentation, now available on-demand, Microsoft’s Amit Kumar discusses 3D IC verification flows with a focus…

Taking 2.5D/3D IC physical verification to the next level

Taking 2.5D/3D IC physical verification to the next level

Taking 2.5D/3D IC physical verification to the next level. As package designs continue to evolve, so must the verification requirements. Designers working on even the most complex multi-die, multi-chiplet stacked configurations require enhanced checking capabilities to quickly and easily verify that the physical die are placed correctly to ensure proper connectivity and electrical behavior.

A deep dive into HDAP LVS/LVL verification

EDA companies are developing tools and workflows to support HDAP (High-density advanced packaging) LVS/LVL verification. Though the data for achieving “signoff-level” confidence is a work in progress, EDA companies are providing tools that can adapt to different levels of data availability and enable HDAP designers to execute HDAP LVS/LVL flows that are both productive and beneficial.

Siemens 3D IC heterogeneous semiconductor packaging workflows catapult design teams into the future of IC design today.

Workflows for tackling heterogeneous integration of chiplets for 2.5D/3D semiconductor packaging

Workflows for tackling heterogeneous integration of chiplets for 2.5D/3D semiconductor packaging.

Parasitic extraction technologies: Advanced node and 3D-IC design

Advanced nodes and 3D-IC packages require new and enhanced parasitic extraction processes that can resolve a variety of complex parasitic issues in these designs.

Impacts of 3D IC on the future

3D IC technology development started many years ago well before the slowing down of Moore’s law benefits became a topic…

System-level, post-layout electrical analysis for high-density advanced packaging (HDAP)

HDAP designs like FOWLP need post-layout simulation (analog) and post-layout STA (digital) flows to augment basic physical verification DRC and LVS.