Design with Calibre

The industry-leading Calibre toolsuite provides physical verification (DRC), circuit verification (LVS, PEX), and reliability verification (PERC), as well as Calibre DFM optimization, to ensure IC designs will deliver the power, performance, and foundry yield today’s markets demand. Across all process nodes and design styles, innovative functionality ensures the Calibre toolsuite provides accurate, efficient, comprehensive IC verification while minimizing resources and tapeout schedules.

Latest posts

Electromigration protection requires accurate interconnect modeling

August 22, 2016

By Karen Chow, Mentor Graphics Electromigration can destroy an IC before its time. Are your designs safe?

By Design With Calibre

7 MIN READ

Leveraging Reliability-Focused Foundry Rule Decks

August 12, 2016

By Matthew Hogan, Mentor Graphics Using your foundry’s reliability rule deck early on lets you correct reliability issues while they…

By Design With Calibre

4 MIN READ

Pattern Matching In Test and Yield Analysis

August 1, 2016

By Jonathan Muirhead and Geir Eide, Mentor Graphics Analyzing fail data with pattern matching helps companies identify yield limiters faster…

By Design With Calibre

4 MIN READ

Reliability Scoring for the Automotive Market

July 18, 2016

By Jeff Wilson, Mentor Graphics Companies designing automotive electronics must understand how variability affects design quality and reliability.

By Design With Calibre

6 MIN READ

Not yet a fan of fan-out? Why you should be!

July 12, 2016

By John Ferguson, Mentor Graphics FO-WLP combines multiple die from heterogeneous processes into a compact package, and that’s a good…

By Design With Calibre

6 MIN READ

Interconnect Robustness Depends on Scaling for Reliability Analysis

June 29, 2016

By Matthew Hogan, Mentor Graphics Fast simulation and PEX are both crucial to interconnect robustness verification. Can your tools scale…

By Design With Calibre

5 MIN READ

Pattern Matching in Design Verification

June 1, 2016

By Michael White, Mentor Graphics Automated pattern matching can solve a wide range of design verification issues. Are you in…

By Design With Calibre

7 MIN READ

Efficient Parasitic Extraction Techniques for Full-Chip Verification

May 26, 2016

By Yousry Elmaghraby, Mentor Graphics Choosing the best PEX method for your full-chip or SoC design is essential. But how…

By Design With Calibre

6 MIN READ

How Do I ECO a Multi-Patterned Design?

May 11, 2016

By David Abercrombie and Alex Pearson, Mentor Graphics Applying ECOs to multipatterned designs can be a nightmare, unless you plan…

By Design With Calibre

7 MIN READ