Design with Calibre

The industry-leading Calibre toolsuite provides physical verification (DRC), circuit verification (LVS, PEX), and reliability verification (PERC), as well as Calibre DFM optimization, to ensure IC designs will deliver the power, performance, and foundry yield today’s markets demand. Across all process nodes and design styles, innovative functionality ensures the Calibre toolsuite provides accurate, efficient, comprehensive IC verification while minimizing resources and tapeout schedules.

Filter by:

Latest posts

A new path for analog design constraints verification

A new path for analog design constraints verification

December 12, 2016

By Dina Medhat, Mentor Graphics Accurate verification of explicitly-defined analog design constraints is crucial for reliability and performance.

By Design With Calibre
5 MIN READ
Mentor’s Battle of the Photonic Bulge

Mentor’s Battle of the Photonic Bulge

December 8, 2016

By Mitch Heins If silicon photonics verification is a battle to be won, Mentor Graphics is on the front lines…

By Design With Calibre
5 MIN READ
How to classify unique DRC results in Calibre RVE

How to classify unique DRC results in Calibre RVE

December 7, 2016

Activating the Shape Class property in your Calibre RVE tool setup allows you to classify and view errors that share…

By Design With Calibre
< 1 MIN READ
All Together Now: FOWLP in the Foundry

All Together Now: FOWLP in the Foundry

December 5, 2016

By John Ferguson, Mentor Graphics FOWLP design popularity is driving foundries to develop in-house FOWLP flows. How will that affect…

By Design With Calibre
5 MIN READ
How To Navigate Through OPC Simulation Results in Calibre WorkBench

How To Navigate Through OPC Simulation Results in Calibre WorkBench

December 1, 2016

Learn how to quickly and easily scan multiple layers of Calibre OPC simulation results in the Calibre RVE tool for…

By Design With Calibre
< 1 MIN READ
Fill/Cut Self-Aligned Double-Patterning

Fill/Cut Self-Aligned Double-Patterning

November 28, 2016

By David Abercrombie, Rehab Ali, Ahmed Hamed-Fatehy, and Shetha Nolke How the SID-SADP process affects your design decisions –

By Design With Calibre
11 MIN READ
Creating An Accurate FEOL CMP Model

Creating An Accurate FEOL CMP Model

November 21, 2016

By Ruben Ghulghazaryan, Jeff Wilson, and Ahmed AbouZeid FEOL CMP modeling helps designers and foundries predict CMP hotspots in advanced…

By Design With Calibre
9 MIN READ
Transistor level ESD verification in large SoC designs

Transistor level ESD verification in large SoC designs

October 31, 2016

Dina Medhat, Mentor Graphics ESD protection is critical, but difficult to verify. Using voltage propagation and logic-aware checks can help

By Design With Calibre
4 MIN READ
Context-Aware Latch-up Checking

Context-Aware Latch-up Checking

October 17, 2016

By Matthew Hogan, Mentor Graphics Latch-up detection is challenging. Learn how automated LUP checks help you find and eliminate LUP…

By Design With Calibre
5 MIN READ