Latest Posts

Design Rule Checking for Silicon Photonics

Design Rule Checking for Silicon Photonics

By Ruping Cao, Mentor Graphics Verifying silicon photonics designs requires new techniques, like equation-based DRC

Reported Death of Moore’s Law Premature?

Reported Death of Moore’s Law Premature?

By Michael White, Mentor Graphics Is Moore’s Law dying? A look at the latest process node activity and technology

Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

Together At Last – Combining Netlist and Layout Data for Power-Aware Verification

By Beth Martin, with Sridhar Srinivasan, Yi-Ting Lee, and Frank Feng, Mentor Graphics Reliability checks on multiple-power-domain and mixed-signal designs…

MEMS Technology and Manufacturing on the Microscale

MEMS Technology and Manufacturing on the Microscale

By Carey Robertson and Khaled AbouZeid, Mentor Graphics Designers incorporating MEMS devices into high-volume CMOS ICs need new processes, data,…

Deja Vu for CMP Modeling?

Deja Vu for CMP Modeling?

By Jeff Wilson, Mentor Graphics With manufacturing innovations and new DFM solutions, CMP modeling is gaining renewed popularity

Assembly Design Kits are the Future of Package Design Verification

Assembly Design Kits are the Future of Package Design Verification

By John Ferguson, Mentor Graphics Like PDKs for ICs, qualified assembly design kits for packages can ensure the quality and…

Parasitic extraction for touchscreen designs

Parasitic extraction for touchscreen designs

By Mohamed ElRefaee, Mentor Graphics Accurate parasitic extraction of touchscreens is essential for ensuring the high-quality performance the market demands

Electrical Overstress Detection and Debugging

Electrical Overstress Detection and Debugging

By Dina Medhat, Mentor Graphics Automated voltage propagation provides an accurate way to detect and correct those hard-to-find EOS conditions…

Case Studies in P&R Double Patterning Debug: Part Two

Case Studies in P&R Double Patterning Debug: Part Two

David Abercrombie continues his expert advice to P&R and chip finishing engineers on understanding and debugging multi-patterning errors accurately and…