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Using Automated Pattern Matching For SRAM Physical Verification

Using Automated Pattern Matching For SRAM Physical Verification

By Elven Huang, Mentor Graphics Accurate SRAM IP verification can be tricky, but automated pattern matching can help.

Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

Using Calibre eqDRC Verification Methodology for Curved Layouts in Silicon Photonics

Calibre eqDRC enables SiP designers to accurately verify non-Manhattan shapes in SiP designs.

Are You (Really) Ready for Your Next Node?

Are You (Really) Ready for Your Next Node?

By Michael White, Mentor Graphics Skipping nodes is gaining popularity, but it can bring some unexpected challenges. Are you prepared?

How to use different Calibre versions for Calibre RealTime and signoff Calibre DRC/LVS jobs

How to use different Calibre versions for Calibre RealTime and signoff Calibre DRC/LVS jobs

In this How-To Video – learn how to run Calibre DRC and LVS jobs from a signoff Calibre version simultaneously…

How to run multiple Calibre RealTime jobs using multiple rule-decks

How to run multiple Calibre RealTime jobs using multiple rule-decks

Need to run multiple rule decks on an AMS design? The Calibre RealTime tool lets you do just that easily…

A Pattern of Success: Calibre Pattern Matching

A Pattern of Success: Calibre Pattern Matching

Calibre Pattern Matching enables innovative DRC and other applications across all process nodes and designs.

How to run Calibre PERC jobs using Calibre Interactive

How to run Calibre PERC jobs using Calibre Interactive

Running Calibre PERC jobs from the Calibre Interactive interface tool only requires a few easy steps. Get the details in…

How to include additional rule files in Calibre Interactive

How to include additional rule files in Calibre Interactive

Want to run custom checks simultaneously with signoff DRC? The Calibre Interactive interface lets you do just that. Learn how…

A new path for analog design constraints verification

A new path for analog design constraints verification

By Dina Medhat, Mentor Graphics Accurate verification of explicitly-defined analog design constraints is crucial for reliability and performance.