Latest Posts

Accurate Lithography Simulation for Silicon Photonics

By Joe Kwan, Mentor Graphics Precise curved geometries are vital to making silicon photonics technology…

Designing and Testing FinFet-based IC Designs

By Carey Robertson and Steve Pateras, Mentor Graphics Are your processes ready for finFETs?…

Self-Aligned Double Patterning, Part Deux

By David Abercrombie, Mentor Graphics Part 2 of a walk-through of the SADP process.  …

Auto IC Market: Revving Up Product Line Means Revving Up Reliability

By Matthew Hogan, Mentor Graphics Designing electronics for automotive use means meeting stringent safety and…

Sign-off lithography simulation and multi-patterning must play well together

By Joe Kwan, Mentor Graphics At 20 nm and below, designers must ensure their lithography…

2-5X Productivity Improvement in 14FDSOI Layout Design: STMicroelectronics Experience with Calibre RealTime

By Atul Bhargava and Mehak Malhotra, STMicroelectronics, India and Srinivas Velivala, Mentor Graphics Rather than…

The Route to Faster Physical Verification and Better Designs

By Nancy Nguyen and Jean-Marie Brunet, Mentor Graphics Using the most accurate and up-to-date signoff…

What about MEMS?

By Carey Robertson, Mentor Graphics With circuit performance driven by capacitance values, accurate calculations are…

A Look Behind the Mask of Multi-Patterning

By Michael White, Mentor Graphics An overview to the mystery of Multi-Patterning…