Impact of Design Size on First Silicon Success This blog is a continuation of a series of blogs related to…
ASIC/IC Power Trends This blog is a continuation of a series of blogs related to the 2014 Wilson Research Group…
If you were not one of the 100’s of visitors to the Verification Academy booth at DAC 2015 and missed…
Still having fun doing UVM and Class based debug? Maybe a debug contest will help. I had a contest with…
In a recent post on deepchip.com John Cooley wrote about “Who Knew VIP?”. In addition, Mark Olen wrote about this…
A colleague recently asked me: Has anything changed? Do design teams tape-out nowadays without GLS (Gate-Level Simulation)? And if so,…
“Who Knew?” about verification IP (VIP), was the theme of a recent DeepChip post by John Cooley on December 18. …
My Feb. 4 post introduced Mentor Graphics’ three-step FPGA verification process intended to help design teams get out of the…
As DVCon expands, we at Mentor Graphics have grown our sponsored sessions as well. Would you expect less? In DVCon’s…
