We have talked about how one can go from ‘No to Know VIP’ in my 3 part series and how Questa VIP PCIe Starter Kits make a Verification engineer’s life easy.
Xilinx® recently posted the “UltraScale PCIe PIPE Simulation with Mentor QVIP” YouTube video that demonstrates how easy it is to hook Questa Verification IP to a Xilinx® PCIe IP.
Some key take-aways from the video:
- Generate a PCIe IP using the Xilinx Vivado® tool
- Download the starter kits from Mentor Supportnet
- Use the starter kit to plug in a UVM testbench for your PCIe
- This UVM testbench has scoreboarding and coverage enabled
- Ready to use sequences
- Plug & Run the UVM simulation using PCIe QVIP starter Kit.
- Check the log for generated transactions e.g TLP packets.
I hope you take 10 minutes to check out the video. Bring up of a UVM environment for Xilinx® PCIe IP could not have been easier.
Are you using Xilinx® PCIe IP in your project? If so, try out the PCIe starter kit and let me know how easy it is to get your UVM testbench up and running so you can spend your cycles on Verification.
Looking forward to hearing your comments on the video and the PCIe starter kit.