Thought Leadership

No to Know VIP – Validated!

By Pradeep Salla

We have talked about how one can go from ‘No to Know VIP’ in my 3 part series and how Questa VIP PCIe Starter Kits make a Verification engineer’s life easy.

Xilinx® recently posted the “UltraScale PCIe PIPE Simulation with Mentor QVIP” YouTube video that demonstrates how easy it is to hook Questa Verification IP to a Xilinx® PCIe IP.

Some key take-aways from the video:

  • Generate a PCIe IP using the Xilinx Vivado® tool
  • Download the starter kits from Mentor Supportnet
  • Use the starter kit to plug in a UVM testbench for your PCIe
  • This UVM testbench has scoreboarding and coverage enabled
  • Ready to use sequences
  • Plug & Run the UVM simulation using PCIe QVIP starter Kit.
  • Check the log for generated transactions e.g TLP packets.

I hope you take 10 minutes to check out the video. Bring up of a UVM environment for Xilinx® PCIe IP could not have been easier.

Are you using Xilinx® PCIe IP in your project? If so, try out the PCIe starter kit and let me know how easy it is to get your UVM testbench up and running so you can spend your cycles on Verification.

Looking forward to hearing your comments on the video and the PCIe starter kit.


3 thoughts about “No to Know VIP – Validated!
  • I’m new to UVM, in fact I’ve only known it existed for 3 weeks now. I was able to get the example design up and running and enjoyed not having to wait for the simulation to sit in electric idle for 5 min. Now if I can only get this translated into a current UVM PCIe testbench…

  • Has anyone attempted to run this with PCIe core settings that vary from this example? I am thinking of a PCIe 2.0 x4 or any other configuration. If so, did it compile and run the QVIP UVM pcie_test?

    • Welcome to the world of UVM, Zachary! To get the starter kit for PCIe 2.0 x4, you need to make the following changes:
      – In EP_config_policy.svh file, make the following changes:
      c.agent_descriptor.pcie_details = ‘{version:PCIE_3_0, gen:PCIE_GEN3, if_type:PCIE_PIPE}; => c.agent_descriptor.pcie_details = ‘{version:PCIE_2_0, gen:PCIE_GEN2, if_type:PCIE_PIPE};
      – In tb_params_pkg, changes the LANES parameter to 2 from 8.

      You would have to configure the Questa VIP as per the configuration of DUT. Hope that helps.

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This article first appeared on the Siemens Digital Industries Software blog at