FPGA Verification Technology Adoption Trends
This blog is a continuation of a series of blogs related to the 2016 Wilson Research Group Functional Verification Study (click here). In my previous blog (click here), I focused on the effectiveness of verification in terms of FPGA project schedule and bug escapes. In this blog, I present verification techniques and technologies adoption trends, as identified by the 2016 Wilson Research Group study.
An interesting trend we see in the FPGA space is a continual maturing of its functional verification processes. In fact, we find that the FPGA design space is about where the ASIC/IC design space was five years ago in terms of verification maturity—and it is catching up quickly. A question you might ask is, “What is driving this trend?” In Part 1 of this blog series I showed rising design complexity with the adoption of more advanced FPGA designs, as well as multiple embedded processor architectures targeted at FPGA designs. In addition, I’ve presented trend data that showed an increase in total project time and effort spent in verification (Part 2 and Part 3). My belief is that the industry creating FPGA designs is being forced to mature its functional verification processes to address today’s increasing complexity.
FPGA Simulation Technique Adoption Trends
Let’s begin by comparing FPGA adoption trends related to various simulation techniques from the both the 2012, 2014, and 2016 Wilson Research Group study, as shown in Figure 1.
Figure 1. Simulation-based technique adoption trends for FPGA designs
You can clearly see that the industry is increasing its adoption of various functional verification techniques for FPGA targeted designs. This past year I have spent a significant amount of time in discussions with FPGA project managers around the world. During these discussions, most managers mention the drive to improve verification process within their projects due to rising complexity. The Wilson Research Group data suggest that these claims are valid.
FPGA Formal Technology Adoption Trends
Figure 2 shows the adoption trends for formal property checking and auto-formal techniques.
Figure 2. FPGA Formal Technology Adoption
Our study looked at two forms of formal technology adoption (i.e., formal property checking and automatic formal verification solutions). Examples of automatic formal verification solutions (also referred to as formal apps) include X safety checks, deadlock detection, reset analysis, and so on. The key difference is that for formal property checking the user writes a set of assertions that they wish to prove. Automatic formal verification solutions do not require the user to write assertions. Again, the key take away here is that FPGA projects are maturing their verification processes to address growing design complexity.
In my next blog (click here), I’ll focus on FPGA design and verification language adoption trends, as identified by the 2016 Wilson Research Group study.
Quick links to the 2016 Wilson Research Group Study results
- Prologue: The 2016 Wilson Research Group Functional Verification Study
- Understanding and Minimizing Study Bias (2016 Study)
- Part 1 – FPGA Design Trends
- Part 2 – FPGA Verification Effort Trends
- Part 3 – FPGA Verification Effort Trends (Continued)
- Part 4 – FPGA Verification Effectiveness Trends
- Part 5 – FPGA Verification Technology Adoption Trends
- Part 6 – FPGA Verification Language and Library Adoption Trends
- Part 7 – ASIC/IC Design Trends
- Part 8 – ASIC/IC Resource Trends
- Part 9 – ASIC/IC Verification Technology Adoption Trends
- Part 10 – ASIC/IC Language and Library Adoption Trends
- Part 11 – ASIC/IC Power Management Trends
- Part 12 – ASIC/IC Verification Results Trends
- Conclusion: The 2016 Wilson Research Group Functional Verification Study